Memory circuitry including computational circuitry for performing supplemental functions

Patent metadata

Field	Value
Publication number	US-9442854-B2
Application number	US-201313841042-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Nov 15, 2012
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A computer system includes but is not limited to a primary processing circuitry, a bus coupled to the primary processing circuitry, and memory circuitry coupled to the bus. The memory circuitry is physically separated from the primary processing circuitry. The memory circuitry includes at least one integrated memory circuit and computational circuitry. The at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry. The computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit can be configured for performing supplemental functions at least partially during time periods that are not accessing intervals.

First claim

What is claimed is:

1. A computer system comprising:
primary processing circuitry;
a bus coupled to the primary processing circuitry; and
memory circuitry coupled to the bus, the memory circuitry physically separated from the primary processing circuitry, the memory circuitry configured as at least one integrated memory circuit including at least:
at least one layer of discrete storage cells configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry, the at least one layer of discrete storage cells distributed over a substrate; and
computational circuitry distributed over the at least one layer of discrete storage cells distributed over the substrate, the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals, the computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for concurrently manipulating data in at least two portions of the logic distributed over the at least one layer of discrete storage cells, the concurrently manipulating data in at least two portions of the logic including at least two of:
a first portion of logic reading and decoding at least one address,
a second portion of logic fetching data from the at least one address, and
a third portion of logic performing at least one calculation on the fetched data.

2. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry configured to present supplementally calculated data in coordination with the requested data.

3. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for performing atomic operations in multiple-stages for searching of data stored in the at least one layer of discrete storage cells.

4. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for performing atomic operations in multiple-stages for sorting of data stored in the at least one layer of discrete storage cells.

5. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for performing atomic operations in multiple-stages for accessing and creating indices for databases stored in the at least one layer of discrete storage cells.

6. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for performing atomic operations in multiple-stages for array computations of data stored in the at least one layer of discrete storage cells.

7. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for performing atomic operations in multiple-stages for least squares computations of data stored in the at least one layer of discrete storage cells.

8. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for performing atomic operations in multiple-stages for garbage collection of data stored in the at least one layer of discrete storage cells.

9. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for performing atomic operations in multiple-stages including at least one of maximum, minimum, or equality computations of data stored in the at least one layer of discrete storage cells.

10. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for performing atomic operations in multiple-stages for statistical computations of data stored in the at least one layer of discrete storage cells.

11. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for performing one or more atomic operations on data stored in the at least one layer of discrete storage cells, wherein at least one of the one or more atomic operations is selected to reduce or minimize number of silicon layers in the at least one integrated memory circuit.

12. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for performing one or more atomic operations on data stored in the at least one layer of discrete storage cells, wherein at least one of the one or more atomic operations is selected to reduce or minimize power requirements in the at least one integrated memory circuit.

13. The computer system according to claim 1 , wherein the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals includes:
computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for performing one or more atomic operations on data stored in the at least one layer of discrete storage cells, wherein at least one of the one or more atomic operations is selected to reduce or minimize heat dissipatio

Assignees

• Elwha Llc A Ltd Liability Corp State Delaware
• Elwha Llc

Inventors

• Hyde Roderick A
• Pasch Nicholas F
• Tegreene Clarence T

Classifications

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title