Process based metrology target design

Patent metadata

Field	Value
Publication number	US-10007744-B2
Application number	US-201514941347-A
Country	US
Kind code	B2
Filing date	Nov 13, 2015
Priority date	Nov 17, 2014
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.

First claim

What is claimed is:

1. A method of metrology target design, the method comprising:
providing design parameters for generating a plurality of metrology targets, each metrology target being of different design and designed for use with a lithography process used to fabricate a physical device on a substrate;
designing, by a computer system, a three-dimensional geometrical structure of the metrology targets based on a model of the lithography process and the design parameters for the metrology targets, wherein the model of the lithography process represents a sequence of process steps;
perturbing a parameter of a process step within the sequence of process steps;
applying the process step with the perturbed parameter to the designed plurality of metrology targets;
selecting a subset of metrology targets from the designed plurality of metrology targets based on the application of the process step with the perturbed parameter;
performing a computer simulation, by the computer system, of at least one metrology target of the subset of metrology targets;
visually rendering, on a display connected to the computer system, a gradual formation of the three-dimensional geometric structure of the at least one metrology target at substrate level based on results from the computer simulation; and
generating electronic data to enable fabrication of at least one metrology target of the subset of metrology targets for use with the lithography process, where the electronic data is used in fabrication of the at least one metrology target of the subset of metrology targets.

2. The method of claim 1 , wherein the plurality of metrology targets is designed automatically.

3. The method of claim 2 , wherein the device comprises multiple device layers.

4. The method of claim 3 , wherein each device layer corresponds to a respective sequence of process steps in the overall model of the lithography process.

5. The method of claim 3 , wherein each of the metrology targets comprises a multi-layer configuration corresponding to at least some of the multiple device layers of the device.

6. The method of claim 5 , wherein at least one of the design parameters used for generating the metrology targets comprises a parameter indicating overlay between two device layers of the device.

7. The method of claim 5 , wherein a relationship between two distinct features of a metrology target is provided as a design parameter, such that if one of the distinct features is altered, the other is also automatically altered.

8. The method of claim 7 , wherein the two distinct features belong to two different device layers.

9. The method of claim 2 , wherein each process step is assigned respective process step indicia.

10. The method of claim 9 , wherein each designed metrology target is tagged with the process step indicia to facilitate retrieval of particular designs from a metrology target database containing a plurality of designed metrology targets.

11. The method of claim 1 , further comprising selecting the subset of metrology targets from the designed plurality of metrology targets for which the change in the three-dimensional geometric structure is minimal when the process step with the perturbed parameter is applied.

12. The method of claim 1 , wherein individual process steps include one or more selected from: deposition, photoresist coating, patterning, etching, stripping, and/or planarization.

13. The method of claim 1 , wherein feature dimensions of the metrology target vary during individual process steps reflecting process-induced effects on a post-processed substrate structure.

14. The method of claim 1 , wherein materials used for individual process steps are selected from a material library.

15. The method of claim 14 , wherein the model for the lithography process provides run time estimation of the simulation process once the materials, the individual process steps, and the design parameters of the metrology targets are provided.

16. The method of claim 1 , further comprising, through a viewing editor, providing a user various tools for visualization, the tools including one or more selected from: coloring, shading, rotating, slicing, making device layers transparent, zooming in, and/or zooming out.

17. A computer program product comprising a non-transitory computer readable medium having instructions recorded thereon, the instructions configured to cause a computer system at least to:
obtain design parameters for generating a plurality of metrology targets, each metrology target being of different design and designed for use with a lithography process used to fabricate a physical device on a substrate;
design a three-dimensional geometrical structure of the metrology targets based on a model of the lithography process and the design parameters for the metrology targets, wherein the model of the lithography process represents a sequence of process steps;
perturb a parameter of a process step within the sequence of process steps;
apply the process step with the perturbed parameter to the designed plurality of metrology targets;
select a subset of metrology targets from the designed plurality of metrology targets based on the application of the process step with the perturbed parameter;
perform a computer simulation of at least one metrology target of the subset of metrology targets;
visually render, on a display, a gradual formation of the three-dimensional geometric structure of the at least one metrology target at substrate level based on results from the computer simulation; and
generate electronic data to enable fabrication of at least one metrology target of the subset of metrology targets for use with the lithography process, where the electronic data is used in fabrication of the at least one metrology target of the subset of metrology targets.

18. The computer program product of claim 17 , wherein the instructions are further configured to cause the computer system to select the subset of metrology targets from the designed plurality of metrology targets for which the change in the three-dimensional geometric structure is minimal when the process step with the perturbed parameter is applied.

19. The computer program product of claim 17 , wherein the model for the lithography process provides run time estimation of the simulation process once materials, the individual process steps, and the design parameters of the metrology targets are provided.

20. The computer program product of claim 17 , wherein at least one of the design parameters used for generating the metrology target comprises a parameter indicating overlay between two device layers of the device.

Assignees

• Asml Netherlands Bv

Inventors

• Chen Guangqing
• Bai Shufeng
• Kent Eric Richard
• Lu Yen-Wen
• Tuffy Paul Anthony
• Wang Jen-Shiang
• Zhang Youping
• Zwartjes Gertjan
• Bijlsma Jan Wouter

Classifications

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/20 Primary

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F17/12

  Simultaneous equations {, e.g. systems of linear equations} · CPC title

• G06F30/333

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G03F7/705 Primary

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title