Adaptive temperature and memory parameter throttling

Patent metadata

Field	Value
Publication number	US-10007311-B2
Application number	US-201615237139-A
Country	US
Kind code	B2
Filing date	Aug 15, 2016
Priority date	Aug 15, 2016
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.

First claim

We claim:

1. A method for temperature throttling in a memory device, the method comprising:
determining a health value of the memory device;
modifying a plurality of temperature throttling thresholds based on the health value of the memory device, wherein each of the temperature throttling thresholds comprises a temperature above which the memory device is throttled differently; and
throttling the memory device when a temperature of the memory device exceeds each of the temperature throttling thresholds, wherein the throttling comprises reducing a performance of the memory device by modifying a programming speed or programming voltage, further wherein each of the temperature throttling thresholds are associated with a different modification of the programming speed or programming value.

2. The method of claim 1 wherein the temperature is measured from a temperature sensor in the memory device.

3. The method of claim 1 wherein the health value is determined based on a usage of the memory device, further wherein the usage comprises a number of program/erase (PE) cycles.

4. The method of claim 3 wherein at least some of the temperature throttling thresholds are increased when the PE cycles is low and gradually decreased as the PE cycles increases.

5. The method of claim 1 , wherein the plurality of temperature throttling thresholds comprise different levels of throttling such that as a temperature exceeds higher temperature throttling thresholds, the throttling of the performance is increased.

6. The method of claim 5 , wherein a reduction in performance is increased corresponding to increased temperatures for each of the temperature throttling thresholds.

7. The method of claim 1 wherein the reducing of the performance further comprises delaying command execution, and modifying command handling.

8. The method of claim 1 wherein the memory device comprises NAND memory and the throttling comprises throttling memory device parameters that include at least one of a clock rate, a flash bus speed, a communication methodology, a command type, a command settings, a command verification, speed margins, or operating voltage.

9. A memory device comprising:
a temperature sensor configured to measure a temperature of the memory device;
a test mode matrix with a plurality of testing parameters for the memory device that are dependent on the temperature, wherein the testing parameters comprise at least programming settings; and
throttling circuitry configured to throttle the memory device based on the temperature to reduce a cross temperature, wherein the cross temperature comprises a difference in temperature when writing data and temperature when reading data.

10. The memory device of claim 9 wherein the programming settings comprise a programming speed and a programming voltage, further wherein the testing parameters further comprise command handling, and command execution timing.

11. The memory device of claim 9 wherein the throttling circuitry throttles differently depending on the temperature.

12. The memory device of claim 9 wherein the throttling reduces the difference in temperature between writing and reading data.

13. The memory device of claim 9 wherein the throttle circuitry is configured to reduce power usage, reduce a temperature of the memory device, alter performance to match production drive variability, or improve endurance of the memory device.

14. The memory device of claim 9 wherein the memory device comprises a three-dimensional (3D) memory configuration, and wherein a controller is associated with operation of and storing to the flash memory.

Assignees

• Sandisk Technologies Llc

Inventors

• Raghu Deepak
• Koh Pao-Ling
• Reusswig Philip
• Yip Chris Nga Yee
• Wan Jun
• Li Yan

Classifications

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F1/206 Primary

  comprising thermal management · CPC title

• G06F3/0616

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G11C16/3418 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title