Memory system and method of operating the same

Patent metadata

Field	Value
Publication number	US-2016180946-A1
Application number	US-201514717623-A
Country	US
Kind code	A1
Filing date	May 20, 2015
Priority date	Dec 17, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A memory system includes a memory device, a plurality of memory blocks which include a plurality of memory cells electrically coupled to a plurality of word lines and store data requested from a host; and a controller suitable for programming first data in a first memory cell among the plurality of memory cells based on a write command received from the host, determining a read voltage of the first memory cell, and reading the first data programmed in the first memory cell based on the read voltage in response to a read command received from the host.

First claim

What is claimed is:

1 . A memory system comprising:
a memory device including a plurality of memory blocks which include a plurality of memory cells electrically coupled to a plurality of word lines and store data requested from a host; and a controller suitable for programming first data in a first memory cell among the plurality of memory cells based on a write command received from the host, determining a read voltage of the first memory cell, and reading the first data programmed in the first memory cell based on the read voltage in response to a read command received from the host, wherein the controller determines the read voltage by checking a data program temperature when programming the first data in the first memory cell and checking a data read temperature when reading the programmed first data from the first memory cell.

2 . The memory system according to claim 1 , wherein the controller determines the read voltage by calculating a read voltage offset between a first read voltage at the data program temperature and a second read voltage at the data read temperature, for the first memory cell, and compensating the second read voltage based on the read voltage offset.

3 . The memory system according to claim 2 , wherein the controller checks a first threshold voltage distribution and a first read retry table at the data program temperature, for the first memory cell.

4 . The memory system according to claim 3 wherein the controller reads information on the first read voltage, the first threshold voltage distribution and the first read retry table, from a flag cell included in the memory device.

5 . The memory system according to claim 3 , wherein the controller reads the first data programmed in the first memory cell at read bias levels included in the first read retry table, and determines a read bias level at which the number of read fail bits of the first data is smallest, as the second read voltage.

6 . The memory system according to claim 5 wherein the controller calculates the read voltage offset based on a read bias level difference between the first read voltage and the second read voltage.

7 . The memory system according to claim 5 , wherein the controller checks a second threshold voltage distribution and a second read retry table at the data read temperature, for the first memory cell, based on the second read voltage.

8 . The memory system according to claim 1 , wherein the read command includes information on the data read temperature.

9 . The memory system according to claim 1 , further comprising:
a temperature sensor suitable for sensing the data read temperature, and providing information on the data read temperature to the controller.

10 . A method of operating a memory system, the method comprising:
programming first data based on a write command received from a host, in a first memory cell among a plurality of memory cells which are included in a plurality of blocks of a memory device and are electrically coupled to a plurality of word lines; determining a read voltage of the first memory cell; and reading the first data programmed in the first memory cell, based on the read voltage, in response to a read command received from the host, wherein the determining of the read voltage of the first memory cell comprises: checking a data program temperature when programming the first data in the first memory cell and checking a data read temperature when reading the programmed first data from the first memory cell.

11 . The method according to claim 10 , wherein the determining of the read voltage of the first memory cell further comprises:
calculating a read voltage offset between a first read voltage at the data program temperature and a second read voltage at the data read temperature, for the first memory cell; and compensating the second read voltage based on the read voltage offset, and determining the read voltage of the first memory cell.

12 . The method according to claim 11 , wherein the checking of the data program temperature comprises:
checking a first threshold voltage distribution and a first read retry table at the data program temperature, for the first memory cell.

13 . The method according to claim 12 , wherein the checking of the first threshold voltage distribution and the first read retry table comprises:
reading information on the first read voltage, the first threshold voltage distribution and the first read retry table, from a flag cell included in the memory device.

14 . The method according to claim 12 , wherein the checking of the data read temperature comprises:
reading the first data programmed in the first memory cell at read bias levels included in the first read retry table; and determining a read bias level at which the number of read fail bits of the first data is smallest, as the second read voltage.

15 . The method according to claim 14 , wherein the calculating of the read voltage offset comprises:
calculating the read voltage offset based on a read bias level difference between the first read voltage and the second read voltage.

16 . The method according to claim 14 , wherein the checking of the data read temperature further comprises:
checking a second threshold voltage distribution and a second read retry table at the data read temperature, for the first memory cell, based on the second read voltage.

17 . The method according to claim 10 , wherein the read command includes information on the data read temperature.

18 . The method according to claim 10 , wherein the checking of the data read temperature comprises:
receiving information on the data read temperature from a temperature sensor of the memory device.

19 . A memory system comprising:
a memory device including a plurality of memory blocks which include a plurality of memory cells electrically coupled to a plurality of word lines and store data requested from a host; and a controller suitable for programming first data in a first memory cell among the plurality of memory cells based on a write command received from the host, determining a read voltage of the first memory cell, and reading the first data programmed in the first memory cell based on the read voltage in response to a read command received from the host.

Assignees

• Sk Hynix Inc

Inventors

• Hong Ji-Man

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C29/021

  in voltage or current generators · CPC title