Link Training for Multi-Segment Communication Networks
US-2026081863-A1 · Mar 19, 2026 · US
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Ravid Ran patents
Ravid Ran is listed as an inventor on 41 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Ravid Ran |
| Total patents | 41 |
| First publication | Mar 24, 2015 |
| Latest publication | Mar 19, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Idle power saving
US-2026067110-A1 · Mar 5, 2026 · US
Physical layer synchronization
US-12563511-B2 · Feb 24, 2026 · US
Link training
US-12500830-B2 · Dec 16, 2025 · US
Power state management for fabrics
US-12418393-B2 · Sep 16, 2025 · US
System for efficient link failure management using physical layer transmission
US-2025279926-A1 · Sep 4, 2025 · US
Systems and methods of initiating retransmission requests
US-2025158739-A1 · May 15, 2025 · US
Systems and methods of initiating retransmission requests
US-12244416-B2 · Mar 4, 2025 · US
Physical layer synchronization
US-2024373378-A1 · Nov 7, 2024 · US
Systems and methods of initiating retransmission requests
US-2024333423-A1 · Oct 3, 2024 · US
Recent patents
Latest publications not already listed above.
Dynamic bandwidth connections
US-11921662-B2 · Mar 5, 2024 · US
Link Training for Multi-Segment Communication Networks
US-2024056380-A1 · Feb 15, 2024 · US
Link efficient power state management for multi-segment switched fabrics
US-2024039689-A1 · Feb 1, 2024 · US
Synthesized clock synchronization between network devices
US-11637557-B2 · Apr 25, 2023 · US
Receive-side timestamp accuracy
US-11552871-B2 · Jan 10, 2023 · US
Dynamic bandwidth connections
US-2022283973-A1 · Sep 8, 2022 · US
Synthesized clock synchronization between network devices
US-2022173741-A1 · Jun 2, 2022 · US
Packet scheduling system with desired physical transmission time for packets
US-11336383-B2 · May 17, 2022 · US
Synthesized clock synchronization between network devices
US-11283454-B2 · Mar 22, 2022 · US
Synthesized Clock Synchronization Between Network Devices
US-2022021393-A1 · Jan 20, 2022 · US
Packet scheduling system with desired physical transmission time for packets
US-2021409137-A1 · Dec 30, 2021 · US
Receive-side timestamp accuracy
US-2021392065-A1 · Dec 16, 2021 · US
Multi-chip module rate adjustment
US-11157433-B2 · Oct 26, 2021 · US
Multi-Chip Module Rate Adjustment
US-2021232525-A1 · Jul 29, 2021 · US
Synthesized clock synchronization between networks devices
US-10778406-B2 · Sep 15, 2020 · US
Synthesized Clock Synchronization Between Network Devices
US-2020169379-A1 · May 28, 2020 · US
Optimizing buffer allocation for network flow control
US-10205683-B2 · Feb 12, 2019 · US
Facilitating communication of data packets using credit-based flow control
US-10079782-B2 · Sep 18, 2018 · US
Data forwarding with speculative error correction
US-10057017-B2 · Aug 21, 2018 · US
Physical-layer signaling of flow control updates
US-9876727-B2 · Jan 23, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Mellanox Technologies Ltd | 29 |
| Mellanox Tech Tlv Ltd | 11 |
| Mellanox Tech Tlv Ltd | 1 |
| Mellanox Technologies Ltd | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H04L1/0041 | 7 |
| H04L1/0045 | 7 |
| H04L47/30 | 6 |
| H04J3/0667 | 6 |
| H04L1/0061 | 5 |