Synthesized clock synchronization between networks devices

Patent metadata

Field	Value
Publication number	US-10778406-B2
Application number	US-201816199312-A
Country	US
Kind code	B2
Filing date	Nov 26, 2018
Priority date	Nov 26, 2018
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

First claim

What is claimed is:

1. A network device comprising:
frequency generation circuitry configured to generate a clock signal;
a phase-locked loop (PLL) configured to generate a local clock based on the clock signal;
a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream; and
a controller configured to:
identify the remote clock recovered by one of the plurality of receivers as a master clock;
find a clock differential between the identified remote clock and the local clock; and
provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential,

wherein the device further comprises a first core die and a second core die, the first core die and the second core die being different dies, the first core die including switching circuitry, and the second core die including the plurality of receivers.

2. The device according to claim 1 , wherein each one receiver of the plurality of receivers is configured to compute a difference between the recovered remote clock of the one receiver and the local clock.

3. The device according to claim 1 , wherein the frequency generation circuitry includes an oscillator.

4. The device according to claim 3 , wherein the frequency generation circuitry includes a frequency mixer configured to combine the control signal from the controller with an output from the oscillator yielding the clock signal as a combined signal for output towards the PLL.

5. The device according to claim 4 , further comprising switching circuitry configured to switch between: connecting the output of the oscillator to the PLL; and connecting an output of the frequency mixer to the PLL.

6. The device according to claim 5 , wherein the controller is configured to provide a control signal to the switching circuitry to switch to connecting the output of the frequency mixer to the PLL when the absolute value of the clock differential is greater than a given value.

7. The device according to claim 5 , wherein the switching circuitry comprises a multiplexer.

8. The device according to claim 4 , further comprising a clock clean-up PLL disposed between an output of the frequency mixer and an input of the PLL to remove jitter from the combined signal.

9. The device according to claim 4 , further comprising a shaper disposed between the controller and the frequency mixer to delay receipt, by the frequency mixer, of the control signal provided by the controller.

10. The device according to claim 1 , wherein the frequency generation circuitry comprises a voltage-controlled oscillator.

11. The device according to claim 1 , wherein the network device comprises a network switch or a network router.

12. A clock synchronization method comprising:
providing a first core die and a second core die, the first core die and the second core die being different dies, the first core die including switching circuitry and the second core die including a plurality of receivers;
generating a clock signal;
generating a local clock based on the clock signal;
receiving, at the plurality of receivers, a plurality of data streams from respective remote clock sources, the plurality of receivers each receiving a respective data stream from a respective remote clock source;
the plurality of receivers each recovering a remote clock from each respective data stream;
identifying the remote clock recovered from one of the plurality of data streams as a master clock;
finding a clock differential between the identified remote clock and the local clock; and
providing a control signal which causes adjustment of the clock signal so as to iteratively reduce an absolute value of the clock differential.

13. The method according to claim 12 , further comprising, for each of the plurality of data streams, computing a difference between the recovered remote clock and the local clock.

14. The method according to claim 12 , further comprising combining the control signal with an output from an oscillator yielding the clock signal as a combined signal.

15. The method according to claim 14 , further comprising switching between using the output of the oscillator as the clock signal; and using the combined signal as the clock signal.

16. The method according to claim 15 , further comprising switching to using the combined signal as the clock signal when the absolute value of the clock differential is greater than a given value.

17. The method according to claim 14 , further comprising removing jitter from the combined signal.

18. The method according to claim 14 , further comprising delaying receipt of the control signal.

Assignees

• Mellanox Technologies Ltd

Inventors

• Gaist Chen
• Ravid Ran
• Berg Aviv
• Koch Lavi

Classifications

• H04L7/04 Primary

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title

• H04J3/0697 Primary

  Synchronisation in a packet node · CPC title