Data forwarding with speculative error correction

Patent metadata

Field	Value
Publication number	US-10057017-B2
Application number	US-201715470928-A
Country	US
Kind code	B2
Filing date	Mar 28, 2017
Priority date	Sep 30, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.

First claim

The invention claimed is:

1. Communication apparatus, comprising:
a data link layer interface, which is configured to perform link-layer processing functions on data packets received over a communication link;
a buffer, which is configured to hold data for output to the data link layer interface; and
a physical layer (PHY) interface, comprising:
an input circuit, which is configured to receive over the communication link a sequence of symbols arranged in a series of data blocks, which encode the data packets, the symbols in each data block comprising a first set of data symbols that encode the data, and a second set of forward error correction (FEC) symbols that encode an error correction code computed over the data encoded in the data block, and to decode the data encoded by the data symbols and pass the decoded data to the buffer irrespective of the FEC symbols; and
an error correction circuit, which is coupled to receive the data and the error correction code from the input circuit, to detect and correct errors in the data using the error correction code so as to generate corrected data, and upon detecting an error in a given data block in the series, to pass the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer,
wherein the error correction circuit is configured to check each of the data blocks for the errors and to output a signal to the data link layer interface indicating whether each of the data blocks was error-free or erroneous, and the data link layer interface is configured to read the data from the buffer or wait for correction depending upon the signal.

2. The apparatus according to claim 1 , wherein the error correction circuit is configured to compute a corrected data block within a predefined computation time, and to check for the errors and output the signal with respect to any particular data block in the series within a detection time that is less than half the predefined computation time.

3. The apparatus according to claim 1 , wherein the error correction circuit is configured to check for the errors and output the signal with respect to any particular data block within a detection time that is no greater than a write time required for the data in the particular data block to be decoded by the input circuit and transferred to the buffer.

4. The apparatus according to claim 1 , and comprising a multiplexer, which has an output coupled to the buffer, a first input coupled to receive the data from the input circuit, and a second input coupled to receive the corrected data from the error correction circuit, and is configured to select the first input as long as the data blocks are error-free and, upon detection of an erroneous data block by the error correction circuit, to select the second input so that the corrected data is output from the multiplexer to the buffer.

5. The apparatus according to claim 4 , wherein selecting the second input causes the corrected data to overwrite the data previously decoded from the given data block and passed by the input circuit to the buffer.

6. A method for communication, comprising:
receiving in a physical layer (PHY) interface over a communication link a sequence of symbols arranged in a series of data blocks, the symbols in each data block comprising a first set of data symbols that encode the data, and a second set of forward error correction (FEC) symbols that encode an error correction code computed over the data encoded in the data block;
decoding, in the PHY interface, the data encoded by the data symbols and passing the decoded data, irrespective of the FEC symbols, to a buffer for output to a data link layer interface, which performs link-layer processing functions on data packets received over the communication link;
concurrently with passing the decoded data to the buffer, detecting errors in the data using the error correction code;
correcting the errors using the error correction code so as to generate corrected data; and
upon detecting an error in a given data block in the series, passing the corrected data from the given data block from the PHY interface to the buffer for output to the data link layer interface in place of the data from the given data block that were previously decoded and passed to the buffer,
wherein detecting the errors comprises checking each of the data blocks for the errors and to outputting a signal to the data link layer interface indicating whether each of the data blocks was error-free or erroneous, and the data link layer interface reads the data from the buffer or waits for correction depending upon the signal.

7. The method according to claim 6 , wherein correcting the errors comprises computing a corrected data block within a predefined computation time, and wherein detecting the errors comprises checking for the errors and outputting the signal with respect to any particular data block in the series within a detection time that is less than half the predefined computation time.

8. The method according to claim 6 , wherein detecting the errors comprises checking for the errors and outputting the signal with respect to any particular data block within a detection time that is no greater than a write time required for the data in the particular data block to be decoded and transferred to the buffer.

9. The method according to claim 6 , and comprising applying the decoded data to a first input of a multiplexer, and applying the corrected data to a second input of the multiplexer, and select the first input for output to the buffer as long as the data blocks are error-free and, upon detection of an erroneous data block, selecting the second input so that the corrected data is output from the multiplexer to the buffer.

10. The method according to claim 9 , wherein selecting the second input causes the corrected data to overwrite the data previously decoded from the given data block and passed by the input circuit to the buffer.

Assignees

• Mellanox Tech Tlv Ltd

Inventors

• Mula Liron
• Ravid Ran
• Wertheim Oded
• Sela Ran
• Kriss Roy

Classifications

• H04L1/16 Primary

  in which the return channel carries supervisory signals, e.g. repetition request signals · CPC title

• H04L69/324 Primary

  in the data link layer [OSI layer 2], e.g. HDLC · CPC title

• H04L1/0052

  Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables · CPC title

• H04L1/0041

  Arrangements at the transmitter end · CPC title

• H04L1/0045

  Arrangements at the receiver end · CPC title