Automatic performance characterization of a network-on-chip (NOC) interconnect
US-10528682-B2 · Jan 7, 2020 · US
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Raponi Pier Giorgio patents
Raponi Pier Giorgio is listed as an inventor on 11 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Raponi Pier Giorgio |
| Total patents | 11 |
| First publication | Oct 8, 2015 |
| Latest publication | Jan 7, 2020 |
Notable patents
Publications ranked by popularity score, then publication date.
Generation of network-on-chip layout based on user specified topological constraints
US-10218581-B2 · Feb 26, 2019 · US
Generation of network-on-chip layout based on user specified topological constraints
US-10050843-B2 · Aug 14, 2018 · US
Systems and methods for selecting a router to connect a bridge in the network on chip (NoC)
US-9762474-B2 · Sep 12, 2017 · US
Automatic performance characterization of a network-on-chip (noc) interconnect
US-2017061041-A1 · Mar 2, 2017 · US
Generation of network-on-chip layout based on user specified topological constraints
US-2017063639-A1 · Mar 2, 2017 · US
Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements
US-9529400-B1 · Dec 27, 2016 · US
Transactional traffic specification for network-on-chip design
US-9473359-B2 · Oct 18, 2016 · US
System and method for visualization of NoC performance based on simulation output
US-9444702-B1 · Sep 13, 2016 · US
Transactional traffic specification for network-on-chip design
US-2015358211-A1 · Dec 10, 2015 · US
Recent patents
Latest publications not already listed above.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Netspeed Systems | 11 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H04L41/145 | 5 |
| H04L49/109 | 4 |
| G06F30/00 | 3 |
| H04L41/12 | 3 |
| H04L45/126 | 2 |