Automatic performance characterization of a network-on-chip (NOC) interconnect

Patent metadata

Field	Value
Publication number	US-10528682-B2
Application number	US-201414477764-A
Country	US
Kind code	B2
Filing date	Sep 4, 2014
Priority date	Sep 4, 2014
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

Methods, systems, and non-transitory computer readable medium for automatically characterizing performance of a System-on-Chip (SoC) and/or Network-on-Chip (NoC) with respect to latency and throughput attributes of one or more traffic flows/profiles under varying traffic load conditions. The characterization of performance may involve a plot representative of latency and throughput, depending on the desired implementation.

First claim

What is claimed is:

1. A non-transitory computer readable medium storing instructions for executing a process, the instructions comprising:
characterizing performance of a Network on Chip (NoC) or a System on Chip (SoC) based on one or more traffic profiles comprising associated one or more heterogeneous traffic flows, and at least one of a NoC model and a SoC model, by:
performing one or more performance simulations for at least a subset of the associated one or more flows at one or more load levels; and
measuring at least one of latency and throughput for the at least the subset of the associated one or more heterogeneous flows;
wherein an initial load level is used for a first one of the one or more performance simulations and a number of subsequent performance simulations to be executed, wherein load levels for the subsequent performance simulations are to be determined based on the latency and the throughput gradients between the prior performance simulations in comparison with a latency curve and a throughput curve, wherein an acceptable latency value for the NoC or the SoC is to be determined based at least in part on a latency value that is a variance delta greater than an ideal latency value on the latency curve, wherein an acceptable throughput value for the NoC or the SoC is to be determined based at least in part on a throughput value that is a variance delta lesser than an ideal throughput value on the throughput curve.

2. The non-transitory computer readable medium of claim 1 , wherein the one or more load levels comprise a first load and a second load, the second load being higher than the first load, and wherein a number of the one or more performance simulations and load levels chosen for each of the one or more performance simulations is determined starting from the first load to the second load.

3. The non-transitory computer readable medium of claim 1 , wherein at least one of the one or more load levels for the one or more flows is different from another one of the one or more load levels for another one of the one or more flows.

4. The non-transitory computer readable medium of claim 1 , wherein the instructions further comprise plotting the at least one of the latency and the throughput from the first load to the second load for the at least the subset of the associated one or more heterogeneous flows.

5. The non-transitory computer readable medium of claim 1 , wherein the instructions further comprise plotting at least one of a latency statistic and a throughput statistic from the first load to the second load for the at least the subset of the associated one or more heterogeneous flows.

6. The non-transitory computer readable medium of claim 1 , wherein the instructions further comprise processing a new traffic profile from the one or more traffic profiles, and performing the performance simulation for one or more flows associated with the new traffic profile from a first load to a second load, the second load being higher than the first load.

7. The non-transitory computer readable medium of claim 1 , wherein the instructions further comprise identifying a load capacity of the NoC or the SoC for at least the subset of the associated one or more heterogeneous flows based on the at least one of the measured latency and throughput.

8. The non-transitory computer readable medium of claim 1 , wherein the at least the subset of the associated one or more heterogeneous flows subset of flows is selected based on an association to the at least one of the NoC and SoC agents.

9. The non-transitory computer readable medium of claim 1 , wherein the at least the subset of the associated one or more heterogeneous flows is selected based on one or more specified properties.

10. The non-transitory computer readable medium of claim 1 , wherein a plurality of the one or more heterogeneous traffic flows is to form part of an interconnect architecture.

11. The non-transitory computer readable medium of claim 1 , wherein each of the one or more heterogeneous traffic flows comprises a different rate attribute, packet size attribute, and Quality of Service (QoS) attribute.

12. A method comprising:
characterizing performance of a Network on Chip (NoC) or a System on Chip (SoC) based on one or more traffic profiles comprising associated one or more heterogeneous traffic flows, and at least one of a NoC model and a SoC model, by:
performing one or more performance simulations for at least a subset of the associated one or more flows at one or more load levels; and
measuring at least one of latency and throughput for the at least the subset of the associated one or more heterogeneous flows;
wherein an initial load level is used for a first one of the one or more performance simulations and a number of subsequent performance simulations to be executed, wherein load levels for the subsequent performance simulations are to be determined based on the latency and the throughput gradients between the prior performance simulations in comparison with a latency curve and a throughput curve, wherein an acceptable latency value for the NoC or the SoC is determined based at least in part on a latency value that is a variance delta greater than an ideal latency value on the latency curve, wherein an acceptable throughput value for the NoC or the SoC is determined based at least in part on a throughput value that is a variance delta lesser than an ideal throughput value on the throughput curve.

13. The method of claim 12 , wherein the one or more load levels comprise a first load and a second load, the second load being higher than the first load, and wherein a number of the one or more performance simulations and load levels chosen for each of the one or more performance simulations is determined starting from the first load to the second load.

14. The method of claim 12 , wherein at least one of the one or more load levels for the one or more flows is different from another one of the one or more load levels for another one of the one or more flows.

15. The method of claim 12 , further comprising plotting the at least one of the latency and the throughput from the first load to the second load for the at least the subset of the associated one or more heterogeneous flows.

16. The method of claim 12 , further comprising plotting at least one of a latency statistic and a throughput statistic from the first load to the second load for the at least the subset of the associated one or more heterogeneous flows.

17. The method of claim 12 , further comprising processing a new traffic profile from the one or more traffic profiles, and performing the performance simulation for one or more flows associated with the new traffic profile from a first load to a second load, the second load being higher than the first load.

18. The method of claim 12 , further comprising identifying a load capacity of the NoC or the SoC for at least the subset of the associated one or more heterogeneous flows based on the at least one of the measured latency and throughput.

19. The method of claim 12 , wherein the at least the subset of the associated one or more heterogeneous flows subset of flows is selected based on an association to the at least one of the NoC and SoC agents.

20. The method of claim 12 , wherein the at least the subset of the associated one or more heterogeneous flows is selected based on one or more specified properties.

Assignees

• Netspeed Systems

Inventors

• Kumar Sailesh
• Norige Eric
• Raponi Pier Giorgio

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F17/5009 Primary

  Physics · mapped topic

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/3947 Primary

  global · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title