Generation of network-on-chip layout based on user specified topological constraints

US10050843B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10050843-B2
Application numberUS-201514625132-A
CountryUS
Kind codeB2
Filing dateFeb 18, 2015
Priority dateFeb 18, 2015
Publication dateAug 14, 2018
Grant dateAug 14, 2018

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  1. Title

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  5. First independent claim

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Abstract

Official abstract text for this publication.

In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and links thereof, can be input by a user in real space, and can then be projected on the grid layout.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: projecting Network on Chip (NoC) elements of a NoC to a grid layout based on specified topological information; and automatically generating the NoC from the projection of the NoC elements to the grid layout; wherein the projecting NoC elements of the NoC to the grid layout based on the specified topological information comprises: projecting a plurality of nodes, a plurality of routers and a plurality of links onto the grid layout based on the specified topological information, wherein the projected plurality of routers, the plurality of nodes, and the plurality of links are disabled; selectively enabling ones of the plurality of routers, ones of the plurality of nodes, and ones of the plurality of links on the grid layout based on one or more constraints for one or more layers of the NoC; providing NoC agents on enabled ones of the plurality of nodes of the grid layout; providing traffic between the provided NoC agents; and mapping the traffic to the enabled ones of the plurality of routers and the plurality of links of the NoC. 2. A non-transitory computer readable medium, storing instructions for executing a process, the instructions comprising: projecting Network on Chip (NoC) elements of a NoC to a grid layout based on specified topological information; and automatically generating the NoC from the projection of the NoC elements to the grid layout; wherein the projecting NoC elements of the NoC to the grid layout based on the specified topological information comprises: projecting a plurality of nodes, a plurality of routers and a plurality of links onto the grid layout based on the specified topological information, wherein the projected plurality of routers, the plurality of nodes, and the plurality of links are disabled; selectively enabling ones of the plurality of routers, ones of the plurality of nodes, and ones of the plurality of links on the grid layout based on one or more constraints for one or more layers of the NoC; providing NoC agents on enabled ones of the plurality of nodes of the grid layout providing traffic between the provided NoC agents; and mapping the traffic to the enabled ones of the plurality of routers and the plurality of links of the NoC.

Assignees

Inventors

Classifications

  • Computer-aided design [CAD] · CPC title

  • Discovery or management of network topologies · CPC title

  • H04L41/145Primary

    involving simulating, designing, planning or modelling of a network · CPC title

  • Physics · mapped topic

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What does patent US10050843B2 cover?
In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and links thereof, can be input by a user in real space…
Who is the assignee on this patent?
Netspeed Systems
What technology area does this patent fall under?
Primary CPC classification H04L41/145. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 14 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).