Techniques to manage execution of divergent shaders
US-11776195-B2 · Oct 3, 2023 · US
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Raoux Thomas F patents
Raoux Thomas F is listed as an inventor on 18 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Raoux Thomas F |
| Total patents | 18 |
| First publication | May 19, 2016 |
| Latest publication | Oct 3, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Techniques to manage execution of divergent shaders
US-2022068005-A1 · Mar 3, 2022 · US
Techniques to manage execution of divergent shaders
US-11107263-B2 · Aug 31, 2021 · US
Facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance at computing devices
US-10796397-B2 · Oct 6, 2020 · US
Method and apparatus for efficient processing of derived uniform values in a graphics processor
US-10726605-B2 · Jul 28, 2020 · US
Techniques to manage execution of shaders
US-2020151936-A1 · May 14, 2020 · US
Reducing memory latency in graphics operations
US-10552934-B2 · Feb 4, 2020 · US
Method and apparatus for subdividing shader workloads in a graphics processor for efficient machine configuration
US-10360717-B1 · Jul 23, 2019 · US
Method and apparatus for subdividing shader workloads in a graphics processor for efficient machine configuration
US-2019206110-A1 · Jul 4, 2019 · US
Hardware instruction set to replace a plurality of atomic operations with a single atomic operation
US-10318292-B2 · Jun 11, 2019 · US
Recent patents
Latest publications not already listed above.
Method and apparatus for efficient processing of derived uniform values in a graphics processor
US-2019087998-A1 · Mar 21, 2019 · US
Specialized code paths in gpu processing
US-2019066256-A1 · Feb 28, 2019 · US
Specialized code paths in GPU processing
US-10140678-B2 · Nov 27, 2018 · US
Reducing memory latency in graphics operations
US-2018005345-A1 · Jan 4, 2018 · US
Increasing Thread Payload for 3D Pipeline with Wider SIMD Execution Width
US-2017178384-A1 · Jun 22, 2017 · US
Apparatus and method for efficient prefix sum operation
US-9632979-B2 · Apr 25, 2017 · US
Facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance at computing devices
US-2016364828-A1 · Dec 15, 2016 · US
Hardware instruction set to replace a plurality of atomic operations with a single atomic operation
US-2016139934-A1 · May 19, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 17 |
| Venkatesh Jayashree | 1 |
| Chen Gang | 1 |
| Raoux Thomas F | 1 |
| Lueh Guei-Yuan | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06T15/005 | 11 |
| G06T1/20 | 10 |
| G06F9/38 | 5 |
| G06F9/3851 | 5 |
| G06T15/80 | 5 |