Reducing memory latency in graphics operations

Patent metadata

Field	Value
Publication number	US-10552934-B2
Application number	US-201615201163-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Jul 1, 2016
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Methods and apparatus relating to reducing memory latency in graphics operations are described. In an embodiment, uniform data is transferred from a buffer to a General Register File (GRF) of a processor based at least in part on information stored in a gather table. The uniform data comprises data that is uniform across a plurality of primitives in a graphics operation. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
a first logic circuitry to transfer uniform data from a buffer to a General Register File (GRF) of a processor based at least in part on information stored in a gather table,
wherein the uniform data is data that is uniform across a plurality of primitives in a graphics operation, wherein, in response to receipt of a drawing operation, data is copied to the buffer from a push buffer, wherein, upon thread dispatch for a program, the uniform data is transferred from the buffer to the GRF, wherein the push buffer stores data from a plurality of constant buffers based at least in part on one or more locations of the uniform data in the plurality of constant buffers and an order in which each portion of the uniform data is transferred to the GRF, wherein the gather table stores information corresponding to a variable size as well as the order in which each portion of the uniform data is transferred to the GRF.

2. The apparatus of claim 1 , wherein the buffer is a Unified Return Buffer (URB) of the processor.

3. The apparatus of claim 2 , wherein the first logic circuitry is to transfer the uniform data from the URB to the GRF.

4. The apparatus of claim 2 , wherein the transferred uniform data is passed to one or more higher frequency operations.

5. The apparatus of claim 2 , wherein the URB is to store data corresponding to a plurality of threads executing on the processor.

6. The apparatus of claim 1 , wherein an on-die memory comprises the buffer.

7. The apparatus of claim 1 , comprising a second logic to gather the uniform data from a plurality of locations in a memory and to store the gathered uniform data in the buffer.

8. The apparatus of claim 7 , wherein the second logic is to perform the gather and store operations in batches.

9. The apparatus of claim 8 , wherein the batches are to cause gathering of all uniform data for an entire render pass.

10. The apparatus of claim 7 , wherein the second logic is to perform the gather and store operations once per draw for three-dimensional graphics operations.

11. The apparatus of claim 7 , wherein the second logic is to perform the gather and store operations once per dispatch for general purpose operations.

12. The apparatus of claim 1 , wherein the buffer is to store a plurality of portions of the uniform data contiguously.

13. The apparatus of claim 1 , wherein the processor is one or more of: a Graphics Processing Unit (GPU) and a processor core.

14. The apparatus of claim 13 , wherein the GPU comprises one or more graphics processing cores.

15. The apparatus of claim 1 , wherein the processor comprises one or more processor cores.

16. The apparatus of claim 1 , wherein the processor comprises at least a portion of the buffer.

17. The apparatus of claim 1 , wherein the processor and the buffer are on a single integrated circuit die.

18. The apparatus of claim 1 , wherein the gather table is to store information corresponding to one or more locations of one or more portions of the uniform data in one or more constant buffers of the plurality of constant buffers.

19. A method comprising:
transferring uniform data from a buffer to a General Register File (GRF) of a processor based at least in part on information stored in a gather table,
wherein the uniform data comprises data that is uniform across a plurality of primitives in a graphics operation, wherein, in response to receipt of a drawing operation, data is copied to the buffer from a push buffer, wherein, upon thread dispatch for a program, the uniform data is transferred from the buffer to the GRF, wherein the push buffer stores data from a plurality of constant buffers based at least in part on one or more locations of the uniform data in the plurality of constant buffers and an order in which each portion of the uniform data is transferred to the GRF, wherein the gather table stores information corresponding to a variable size as well as the order in which each portion of the uniform data is transferred to the GRF.

20. The method of claim 19 , wherein the buffer comprises a Unified Return Buffer (URB) of the processor.

21. The method of claim 19 , further comprising gathering the uniform data from a plurality of locations in a memory and to storing the gathered uniform data in the buffer.

22. The method of claim 19 , wherein the gather table is to store information corresponding to one or more locations of one or more portions of the uniform data in one or more constant buffers of the plurality of constant buffers.

23. One or more non-transitory computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
transfer uniform data from a buffer to a General Register File (GRF) of the processor based at least in part on information stored in a gather table,
wherein the uniform data comprises data that is uniform across a plurality of primitives in a graphics operation, wherein, in response to receipt of a drawing operation, data is copied to the buffer from a push buffer, wherein, upon thread dispatch for a program, the uniform data is transferred from the buffer to the GRF, wherein the push buffer stores data from a plurality of constant buffers based at least in part on one or more locations of the uniform data in the plurality of constant buffers and an order in which each portion of the uniform data is transferred to the GRF, wherein the gather table stores information corresponding to a variable size as well as the order in which each portion of the uniform data is transferred to the GRF.

24. The one or more non-transitory computer-readable medium of claim 23 , wherein the buffer comprises a Unified Return Buffer (URB) of the processor.

25. The one or more non-transitory computer-readable medium of claim 23 , wherein the gather table is to store information corresponding to one or more locations of one or more portions of the uniform data in one or more constant buffers of the plurality of constant buffers.

Assignees

• Intel Corp

Inventors

• Apodaca Michael
• Cimini David M
• Raoux Thomas F
• Ghosh Somnath
• Mukherjee Uddipan
• Bose Debraj
• Deka Sthiti
• Gevim Yohai

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0886

  Variable-length word access · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06T15/80

  Shading · CPC title