Specialized code paths in GPU processing

Patent metadata

Field	Value
Publication number	US-10140678-B2
Application number	US-201615089270-A
Country	US
Kind code	B2
Filing date	Apr 1, 2016
Priority date	Dec 18, 2015
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

Techniques to improve graphics processing unit (GPU) performance by introducing specialized code paths to process frequent common values are described. A shader compiler can determine instruction that, during operation, may output a common value and can introduce an enhanced shader instruction branch to process the common value to reduce overall computational requirements to execute the shader.

First claim

What is claimed is:

1. An apparatus to compile a shader comprising:
logic, at least a portion of which is implemented in hardware, the logic to:
determine whether an output-merger (OM) state of a shader instruction is set to a src_alpha; and
compile the shader instruction to include an optimized sub-sequence based on a determination that the OM state is set to src_alpha.

2. The apparatus of claim 1 , the logic to:
select the shader instruction that will output a value that matches a predetermined value, wherein the predetermined value comprises one, zero, 1.0 f, or 0.0 f; and
compile the shader instruction to include the optimized sub-sequence based on selection of the shader instruction.

3. The apparatus of claim 2 , the logic to:
evaluate at least one coordinate; and
determine whether the shader instruction can output the predetermined value based on the at least one coordinate.

4. The apparatus of claim 2 , wherein the shader instruction comprises a sample_c instruction, a mul_sat instruction, an add_sat instruction, a ld instruction, a sample instruction, an AND instruction, a greater than instruction, an equal to instruction, or a less than instruction.

5. The apparatus of claim 2 , the logic to generate an optimized shader based in part on compiling the shader instructions, the optimized shader to:
determine whether the output of the shader instruction equals the predetermined value; and
execute a first sequence based on a determination that the output of the shader instruction equals the predetermined value; and
execute a second sequence based on a determination that the output of the shader instruction does not equal the predetermined value, the second sequence requiring more graphics processing resources than the first sequence.

6. The apparatus of claim 2 , the logic to:
determine whether the shader instruction can be folded based on a determination that the shader instruction can output the predetermined value; and
compile the shader instruction to include the optimized sub-sequence based on a determination that the shader instruction can be folded.

7. The apparatus of claim 6 , the logic to compile the shader instruction omitting the optimized sub-sequence based on a determination that the shader instruction cannot be folded.

8. The apparatus of claim 2 , wherein the compiled shaders comprise a pixel shader, a vertex shader, a depth shader, a fragment shader, a domain shader, a hull shader, a computer shader, or a geometry shader.

9. The apparatus of claim 1 , the logic to compile the shader instruction omitting the optimized sub-sequence based on a determination that the OM state is not set to src_alpha.

10. The apparatus of claim 1 , the logic to:
determine whether an alpha-max corresponding to the shader instruction is equal to zero; and
bind the shader based on a determination that the alpha_max corresponding to the shader instruction equals zero.

11. A method comprising:
determining whether an output-merger (OM) state of a shader instruction is set to a src_alpha; and
compiling the shader instruction to include an optimized sub-sequence based on a determination that the OM state is set to src_alpha.

12. The method of claim 11 , comprising:
selecting the shader instruction that will output a value that matches a predetermined value, wherein the predetermined value comprises one, zero, 1.0 f, or 0.0 f; and
compiling the shader instruction to include the optimized sub-sequence based on selection of the shader instruction.

13. The method of claim 12 , comprising:
evaluating at least one coordinate; and
determining whether the shader instruction can output the predetermined value based on the at least one coordinate.

14. The method of claim 12 , wherein the shader instruction comprises a sample_c instruction, a mul_sat instruction, an add_sat instruction, a ld instruction, a sample instruction, an AND instruction, a greater than instruction, an equal to instruction, or a less than instruction.

15. The method of claim 12 , comprising:
determining whether the shader instruction can be folded based on a determination that the shader instruction can output the predetermined value; and
compiling the shader instruction to include the optimized sub-sequence based on a determination that the shader instruction can be folded.

16. The method of claim 15 , comprising compiling the shader instruction omitting the optimized sub-sequence based on a determination that the shader instruction cannot be folded.

17. At least one non-transitory machine-readable storage medium comprising instructions that when executed by a computing device, cause the computing device to:
determine whether an output-merger (OM) state of a shader instruction is set to a src_alpha; and
compile the shader instruction to include an optimized sub-sequence based on a determination that the OM state is set to src_alpha.

18. The at least one non-transitory machine-readable storage medium of claim 17 , comprising instructions that when executed by the computing device, cause the computing device to:
select the shader instruction that will output a value that matches a predetermined value, wherein the predetermined value comprises one, zero, 1.0 f, or 0.0 f; and
compile the shader instruction to include the optimized sub-sequence based on selection of the shader instruction.

19. The at least one non-transitory machine-readable storage medium of claim 18 , comprising instructions that when executed by the computing device, cause the computing device to:
evaluate at least one coordinate; and
determine whether the shader instruction can output the predetermined value based on the at least one coordinate.

20. The at least one non-transitory machine-readable storage medium of claim 18 , wherein the shader instruction comprises a sample_c instruction, a mul_sat instruction, an add_sat instruction, a ld instruction, a sample instruction, an AND instruction, a greater than instruction, an equal to instruction, or a less than instruction.

21. The at least one non-transitory machine-readable storage medium of claim 17 , comprising instruction that when executed by the GPU, cause the GPU to:
evaluate at least one coordinate of pixel;
execute a shader instruction based on the at least one coordinate;
determine whether an output of the shader instruction equals a value that matches a predetermined value, wherein the predetermined value comprises one, zero, 1.0 f, or 0.0 f; and
execute a first sequence based on a determination that the output equals the predetermined value; and
execute a second sequence based on a determination that the output does not equal the predetermined value.

22. The at least one non-transitory machine-readable storage medium of claim 21 , comprising instruction that when executed by the GPU, wherein the shader instruction comprises a sample_c instruction, a mul_sat instruction, an add_sat instruction, a ld instruction, a sample instruction, an AND instruction, a greater than instruction, an equal to instruction, or a less than instruction.

Assignees

• Intel Corp

Inventors

• Sharma Saurabh
• Ventakesh Abhishek
• Schluessler Travis T
• Raoux Thomas F
• Sathe Rahul P
• Hasselgren Jon

Classifications

• G06T15/005

  General purpose rendering architectures · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F8/41 Primary

  Compilation · CPC title

• G06F9/30149

  of variable length instructions · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title