Semiconductor hold time fixing

Patent metadata

Field	Value
Publication number	US-9171112-B2
Application number	US-201314099937-A
Country	US
Kind code	B2
Filing date	Dec 7, 2013
Priority date	Dec 7, 2012
Publication date	Oct 27, 2015
Grant date	Oct 27, 2015

Abstract

Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with hold-time violations are wired later, thus fixing hold-time violations without scaling or adding further buffers. Hold times are re-evaluated once wiring of track routes is complete.

First claim

What is claimed is:

1. A computer-implemented method for design analysis and modification comprising:
evaluating a semiconductor design based on ideal clocks;
estimating hold-time requirements for the design based on the ideal clocks;
allocating, using one or more processors, placement regions for the design wherein the placement regions are to be used during hold-time fixing, wherein the allocating of placement regions to be used during hold-time fixing allows for access to pins on blocks within the design;
wiring track routes for the design wherein the wiring of track routes for hold-time critical nets is performed later than wiring of nets without hold-time violations; and
modifying the design by performing hold-time fixing on the design.

2. The method of claim 1 wherein clock constraints are used as part of the estimating of hold-time requirements.

3. The method of claim 1 further comprising performing placement.

4. The method of claim 3 wherein the placement includes incremental global placement.

5. The method of claim 3 wherein the placement is based on buffers that are inserted as part of the hold-time fixing.

6. The method of claim 1 further comprising estimating a number of buffers required.

7. The method of claim 6 further comprising reserving required routing resources for the number of buffers.

8. The method of claim 1 further comprising placing buffers as part of the hold-time fixing.

9. The method of claim 1 further comprising determining critical clock-gate enable paths.

10. The method of claim 9 wherein the determining of the critical clock-gate enable paths is used in the hold-time fixing.

11. The method of claim 1 further comprising re-evaluating hold times once the wiring of track routes is accomplished.

12. The method of claim 11 further comprising incrementally adjusting buffering to improve hold times.

13. The method of claim 1 further comprising detail routing wires for the design.

14. The method of claim 1 further comprising performing clock-tree synthesis for the design.

15. The method of claim 14 further comprising incrementally removing space remaining in the placement regions that were allocated.

16. A computer system for design analysis and modification comprising:
a memory which stores instructions;
one or more processors coupled to the memory wherein the one or more processors are configured to:
evaluate a semiconductor design based on ideal clocks;
estimate hold-time requirements for the design based on the ideal clocks;
allocate placement regions for the design wherein the placement regions are to be used during hold-time fixing, wherein the allocating of placement regions to be used during hold-time fixing allows for access to pins on blocks within the design;
wire track routes for the design wherein the wiring of track routes for hold-time critical nets is performed later than wiring of nets without hold-time violations; and
modify the design by performing hold-time fixing on the design.

17. The system of claim 16 wherein the wherein the one or more processors are further configured to perform placement where the placement is based on buffers that are inserted as part of the hold-time fixing.

18. The system of claim 16 wherein the wherein the one or more processors are further configured to estimate a number of buffers required and reserve required routing resources for the number of buffers.

19. The system of claim 16 wherein the wherein the one or more processors are further configured to wire track routes for the design and re-evaluate hold times once wiring of track routes is accomplished.

20. A computer program product embodied in a non-transitory computer readable medium for design analysis and modification comprising:
code for evaluating a semiconductor design based on ideal clocks;
code for estimating hold-time requirements for the design based on the ideal clocks;
code for allocating placement regions for the design wherein the placement regions are to be used during hold-time fixing, wherein the allocating of placement regions to be used during hold-time fixing allows for access to pins on blocks within the design;
code for wiring track routes for the design wherein the wiring of track routes for hold-time critical nets is performed later than wiring of nets without hold-time violations; and
code for modifying the design by performing hold-time fixing on the design.

21. The computer program product of claim 20 further comprising code for performing placement where the placement is based on buffers that are inserted as part of the hold-time fixing.

22. The computer program product of claim 20 further comprising code for estimating a number of buffers required and code for reserving required routing resources for the number of buffers.

23. The computer program product of claim 20 further comprising code for re-evaluating hold times once the wiring of track routes is accomplished.

24. The computer program product of claim 23 further comprising code for incrementally adjusting buffering to improve hold times.

25. The system of claim 19 wherein the wherein the one or more processors are further configured to incrementally adjust buffering to improve hold times.

26. The computer program product of claim 20 wherein the hold-time fixing on the design is based on a constant model for signals and clocks.

27. The computer program product of claim 20 wherein the hold-time fixing on the design uses hold-fixing scenarios which are determined and activated prior to placement.

28. The computer program product of claim 20 wherein the hold-time fixing on the design takes into account global models of clocks and signals.

Assignees

• Synopsys Inc

Inventors

• Kalpat Karthik Ramaseshan
• Kumar Rohit
• Nimmagadda Narendra
• Shah Saumil Sanjay
• Tseng Hsiao-Ping

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F17/5031 Primary

  Physics · mapped topic

• G06F30/396

  Clock trees · CPC title