Multithreaded processor core with hardware-assisted task scheduling

Patent metadata

Field	Value
Publication number	US-11360809-B2
Application number	US-201816024343-A
Country	US
Kind code	B2
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Jun 14, 2022
Grant date	Jun 14, 2022

Abstract

Embodiments of apparatuses, methods, and systems for scheduling tasks to hardware threads are described. In an embodiment, a processor includes a multiple hardware threads and a task manager. The task manager is to issue a task to a hardware thread. The task manager includes a hardware task queue to store a descriptor for the task. The descriptor is to include a field to store a value to indicate whether the task is a single task, a collection of iterative tasks, and a linked list of tasks.

First claim

What is claimed is:

1. A processor comprising:
a plurality of hardware threads; and
task manager hardware to issue a new task to a first hardware thread of the plurality of hardware threads;
a hardware task queue to store a descriptor for the new task, the descriptor to include a field to store one of a plurality of values, wherein a first value of the plurality of values is to indicate the new task is a single task, a second value of the plurality of values is to indicate the new task is iterative, and a third value is to indicate the new task is a linked list of tasks; and
a response buffer, wherein the task manager is to check the response buffer for a current task before issuing the new task.

2. The processor of claim 1 , wherein the first hardware thread includes a load/store queue to request the new task from the task manager hardware by issuing a read request to the task manager hardware.

3. The processor of claim 1 , wherein if the one of the plurality of values indicates the new task is iterative, then the descriptor also includes a count value to specify a number of iterations.

4. The processor of claim 1 , wherein if the one of the plurality of values indicates the new task is a linked list of tasks, then the descriptor also includes a pointer to a head of the linked list of tasks.

5. The processor of claim 1 , wherein an instruction set architecture of the first hardware thread of the plurality of hardware threads and an instruction set architecture of a second hardware thread of the plurality of hardware threads are compatible.

6. The processor of claim 5 , further comprising a thread engine to migrate the new task from the first hardware thread to the second hardware thread.

7. The processor of claim 6 , wherein the first hardware thread is in a first single-threaded pipeline and the second hardware thread is in a second single-threaded pipeline.

8. The processor of claim 6 , wherein the first hardware thread and the second hardware thread are in a single multithreaded pipeline.

9. The processor of claim 6 , wherein the first hardware thread is in a first multithreaded pipeline and the second hardware thread is in a second multithreaded pipeline.

10. The processor of claim 6 , wherein only one of the first hardware thread and the second hardware thread is in a single-threaded pipeline and the other of the first hardware thread and the second hardware thread is in a multithreaded pipeline.

11. The processor of claim 8 , wherein the single multithreaded pipeline restricts software threads to one operation outstanding at a time.

12. A method comprising:
requesting, by a hardware thread of a multithreaded processor core, a new task from task manager hardware within the multithreaded processor core;
checking, by the task manager hardware, a response buffer within the multithreaded processor core for a current task before issuing the new task;
reading, from a hardware queue within the multithreaded processor core by the task manager hardware, a descriptor for the new task, the descriptor including one of a plurality of values, wherein a first value of the plurality of values is to indicate the new task is a single task, a second value of the plurality of values is to indicate the new task is iterative, and a third value is to indicate the new task is a linked list of tasks; and
issuing, by the task manager hardware, the new task to the hardware thread.

13. The method of claim 12 , wherein the hardware thread requests the new task from the task manager hardware by sending, by a load/store queue, a read request to the task manager hardware.

14. The method of claim 12 , wherein the descriptor specifies that the new task is a single task type.

15. The method of claim 12 , wherein the descriptor:
specifies that the new task is iterative; and
specifies a count value to indicate a number of iterations.

16. The method of claim 12 , wherein the descriptor:
specifies that the new task is one of a linked list of tasks; and
specifies a pointer to a head of the linked list of tasks.

17. A system comprising:
a processor including:
a plurality of hardware threads; and
task manager hardware to issue a new task to a first hardware thread of the plurality of hardware threads;
a hardware task queue to store a descriptor for the task, the descriptor to include a field to store one of a plurality of values, wherein a first value of the plurality of values is to indicate the new task is a single task, a second value of the plurality of values is to indicate the new task iterative, and a third value is to indicate the new task is a linked list of tasks; and
a response buffer, wherein the task manager is to check the response buffer for a current task before issuing the new task; and

a system memory coupled to the processor, wherein the first hardware thread and a second hardware thread of the plurality of hardware threads have a coherent view of the system memory.

18. The system of claim 17 , wherein the processor is to execute a graph application including a new task; and the processor also includes a thread engine to migrate the new task from the first hardware thread of the plurality of hardware threads to the second hardware thread of the plurality of hardware threads to improve performance of the graph application based on access from the new task to memory.

Assignees

• Intel Corp

Inventors

• Griffin William Paul
• Fryman Joshua
• Howard Jason
• Park Sang Phill
• Pawlowski Robert
• Abbott Michael
• Cline Scott
• Jain Samkit
• More Ankit
• Cave Vincent
• Petrini Fabrizio
• Ganev Ivan

Classifications

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title