Providing memory management functionality using aggregated memory management units (MMUs)
US-10019380-B2 · Jul 10, 2018 · US
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Miretsky Alexander patents
Miretsky Alexander is listed as an inventor on 8 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Miretsky Alexander |
| Total patents | 8 |
| First publication | Oct 20, 2016 |
| Latest publication | Jul 10, 2018 |
Notable patents
Publications ranked by popularity score, then publication date.
Multi-threaded translation and transaction re-ordering for memory management units
US-10007619-B2 · Jun 26, 2018 · US
Burst translation look-aside buffer
US-9836410-B2 · Dec 5, 2017 · US
Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media
US-9824015-B2 · Nov 21, 2017 · US
PROVIDING MEMORY MANAGEMENT FUNCTIONALITY USING AGGREGATED MEMORY MANAGEMENT UNITS (MMUs)
US-2017091116-A1 · Mar 30, 2017 · US
Multi-threaded translation and transaction re-ordering for memory management units
US-2016350234-A1 · Dec 1, 2016 · US
Providing memory management unit (mmu) partitioned translation caches, and related apparatuses, methods, and computer-readable media
US-2016350222-A1 · Dec 1, 2016 · US
Burst translation look-aside buffer
US-2016306746-A1 · Oct 20, 2016 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 8 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/1036 | 6 |
| G06F2212/50 | 6 |
| G06F2212/683 | 4 |
| G06F2212/1016 | 4 |
| G06F2212/1041 | 2 |