Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media

Patent metadata

Field	Value
Publication number	US-9824015-B2
Application number	US-201514725882-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	May 29, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

First claim

What is claimed is:

1. An apparatus comprising a memory management unit (MMU) for providing partitioned translation caches, comprising:
a translation cache configured to provide a plurality of translation cache entries each defining an address translation mapping;
a partition descriptor table configured to provide a plurality of partition descriptors defining a corresponding plurality of partitions of the translation cache, each partition of the plurality of partitions comprising one or more translation cache entries of the plurality of translation cache entries; and
a partition translation circuit configured to:
receive a memory access request from a requestor;
determine a translation cache partition identifier (TCPID) of the memory access request;
identify one or more partitions of the plurality of partitions based on the TCPID; and
perform a cache operation on a translation cache entry of the one or more translation cache entries of the one or more partitions.

2. The apparatus of claim 1 , wherein the partition descriptor table is configured to provide the plurality of partition descriptors each comprising:
a start pointer to a starting translation cache entry of a corresponding partition defined by the partition descriptor; and
an end pointer to an ending translation cache entry of the corresponding partition.

3. The apparatus of claim 1 , wherein the partition descriptor table is configured to provide the plurality of partition descriptors each comprising:
a start pointer to a starting translation cache entry of a corresponding partition defined by the partition descriptor; and
a count indicator indicative of a count of the one or more translation cache entries of the corresponding partition.

4. The apparatus of claim 1 , wherein the partition translation circuit is configured to determine the TCPID by deriving the TCPID based on an attribute of the memory access request.

5. The apparatus of claim 1 , wherein the partition translation circuit is configured to determine the TCPID by retrieving a requestor-supplied TCPID provided by the memory access request.

6. The apparatus of claim 1 , further comprising a partition remapping table configured to provide a plurality of remapping entries each defining a remapping of an input TCPID to an output TCPID;
wherein the partition translation circuit is configured to:
determine the TCPID by identifying a remapping entry of the plurality of remapping entries, in which the input TCPID of the remapping entry corresponds to the TCPID of the memory access request; and
identify the one or more partitions of the plurality of partitions based on the output TCPID of the remapping entry.

7. The apparatus of claim 1 , wherein:
the memory access request comprises a source indicator indicating a source type of the requestor; and
the partition translation circuit is configured to determine the TCPID by deriving the TCPID based on the source indicator.

8. The apparatus of claim 1 , further comprising a partition selection table comprising a plurality of partition selection entries, each defining at least one of a search control indicator and an eviction control indicator, and each corresponding to one or more partitions of the plurality of partitions; and
wherein the partition translation circuit is configured to identify the one or more partitions of the plurality of partitions based on a partition selection entry of the plurality of partition selection entries.

9. The apparatus of claim 8 , wherein the partition translation circuit is configured to perform the cache operation by determining that the one or more translation cache entries of the one or more partitions are eligible for searching based on the search control indicator of the partition selection entry for the one or more partitions.

10. The apparatus of claim 8 , wherein the partition translation circuit is configured to perform the cache operation by determining that the one or more translation cache entries of the one or more partitions are eligible for eviction based on the eviction control indicator of the partition selection entry for the one or more partitions.

11. The apparatus of claim 1 integrated into an integrated circuit (IC).

12. The apparatus of claim 1 integrated into a device selected from a group consisting of a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a music player, and a video player.

13. A memory management unit (MMU) comprising:
a means for providing a plurality of translation cache entries each defining an address translation mapping;
a means for providing a plurality of partition descriptors defining a corresponding plurality of partitions of a translation cache of the MMU, each partition of the plurality of partitions comprising one or more translation cache entries of the plurality of translation cache entries;
a means for receiving a memory access request from a requestor;
a means for determining a translation cache partition identifier (TCPID) of the memory access request;
a means for identifying one or more partitions of the plurality of partitions based on the TCPID; and
a means for performing a cache operation on a translation cache entry of the one or more translation cache entries of the one or more partitions.

14. A method for providing partitioned translation caches, comprising:
receiving, by a memory management unit (MMU), a memory access request from a requestor;
determining a translation cache partition identifier (TCPID) of the memory access request;
identifying, based on the TCPID, one or more partitions of a plurality of partitions of a translation cache of the MMU; and
performing a cache operation on a translation cache entry of one or more translation cache entries of the one or more partitions.

15. The method of claim 14 , wherein identifying the one or more partitions of the plurality of partitions is further based on a corresponding plurality of partition descriptors each comprising:
a start pointer to a starting translation cache entry of a corresponding partition defined by the partition descriptor; and
an end pointer to an ending translation cache entry of the corresponding partition.

16. The method of claim 14 , wherein identifying the one or more partitions of the plurality of partitions is further based on a corresponding plurality of partition descriptors each comprising:
a start pointer to a starting translation cache entry of a corresponding partition defined by the partition descriptor; and
a count indicator indicative of a count of the one or more translation cache entries of the corresponding partition.

17. The method of claim 14 , wherein determining the TCPID comprises deriving the TCPID based on an attribute of the memory access request.

18. The method of claim 14 , wherein determining the TCPID comprises retrieving a requestor-supplied TCPID provided by the memory access request.

19. The method of claim 14 , comprising:
determining the TCPID by identifying a remapping entry among a plurality of remapping entries each defining a remapping of an input TCPID to an output TCPID, in which the input TCPID of the remapping entry corresponds to the TCPID of the memory access request; and
identifying the one or more partitions of the plurality of partitions based on the output TCPID of the remapping entry

Assignees

• Qualcomm Inc

Inventors

• Podaima Jason Edward
• Rychlik Bohuslav
• MOREIRA Carlos Javier
• Gadelrab Serag Monier
• Wiercienski Paul Christopher John
• Miretsky Alexander
• Ernewein Kyle John

Classifications

• G06F2212/69

  Physics · mapped topic

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F2212/601

  Reconfiguration of cache memory · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F2212/1016

  Performance improvement · CPC title