Burst translation look-aside buffer

Patent metadata

Field	Value
Publication number	US-9836410-B2
Application number	US-201514865965-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Apr 15, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A comparand that includes a virtual address is received. Upon determining a match of the comparand to a burst entry tag, a candidate matching translation data unit is selected. The selecting is from a plurality of translation data units associated with the burst entry tag, and is based at least in part on at least one bit of the virtual address. Content of the candidate matching translation data unit is compared to at least a portion of the comparand. Upon a match, a hit is generated.

First claim

What is claimed is:

1. A method for translating a virtual address, comprising
receiving a comparand, wherein the comparand includes a virtual address; and
upon determining a match of the comparand to a burst entry tag,
selecting a candidate matching translation data unit, the selecting being from a plurality of translation data units, the plurality of translation data units being associated with the burst entry tag, the plurality of translation data units being associated with a corresponding plurality of data validity flags, each one of the plurality of data validity flags for indicating validity of a respective one of the plurality of translation data units, and the selecting being based at least in part on at least one bit of the virtual address, and
comparing a content of the candidate matching translation data unit to at least a portion of the comparand and, upon a result of the comparing indicating a match, generating a hit,

wherein the burst entry tag comprises a burst entry validity flag based at least in part on a logical OR of the plurality of data validity flags, and wherein determining that the comparand matches the burst entry tag is based, at least in part on the burst entry validity flag.

2. The method of claim 1 , further comprising storing a burst entry, the burst entry comprising the burst entry tag and the plurality of translation data units.

3. The method of claim 1 , wherein the burst entry tag includes a burst entry address range, and wherein the match of the comparand to the burst entry tag is based, at least in part, on the virtual address being an address within the burst entry address range.

4. The method of claim 3 , wherein the method further comprises:
receiving an invalidation comparand; and
based at least in part on a match of the invalidation comparand to the burst entry tag, invalidating the burst entry corresponding to the burst entry tag.

5. The method of claim 3 , wherein the burst entry address range is a burst entry primary address range, and wherein the burst entry tag further includes a burst entry secondary address range, and wherein the method further comprises:
receiving an invalidation comparand; and
based at least in part on a match of the invalidation comparand to the burst entry secondary address range, invalidating the translation data units that correspond to the burst entry secondary address range.

6. The method of claim 1 , further comprising storing a burst entry, the burst entry comprising the burst entry tag and the plurality of translation data units, wherein the burst entry validity flag is switchable between a burst entry valid flag and a burst entry invalid flag.

7. The method of claim 6 , wherein the burst entry tag includes a burst entry address range, and wherein the match of the comparand to the burst entry tag is further based, at least in part, on the virtual address being an address within the burst entry address range.

8. The method of claim 7 , wherein the method further comprises:
receiving an invalidation comparand; and
based at least in part on a match of the invalidation comparand to the burst entry tag, switching the burst entry validity flag to the burst entry invalid flag.

9. The method of claim 7 , wherein each of the translation data units includes a translation data validity flag, wherein the translation data validity flag is switchable between a translation data valid flag and a translation data invalid flag, and wherein a result of the comparing indicating a match requires that the translation data validity flag of the candidate matching translation data unit is the translation data valid flag.

10. The method of claim 9 , wherein the burst entry address range is a burst entry primary address range, and wherein the burst entry tag further includes a burst entry secondary address range, and wherein the method further comprises:
receiving an invalidation comparand; and
based at least in part on a match of the invalidation comparand to the burst entry secondary address range, switching the translation data validity flag of the candidate matching translation data unit to the translation data invalid flag.

11. The method of claim 1 , wherein the burst entry is among a plurality of burst entries, each of the burst entries comprising a corresponding burst entry tag and a corresponding plurality of translation data units,
wherein the plurality of translation data units of each burst entry includes M translation data units, M being an integer, and
wherein determining whether the comparand matches the burst entry tag comprises determining whether the comparand matches the corresponding burst entry tag of at least one of the burst entries.

12. The method of claim 11 , wherein each of the M translation data units holds mapping information for a span of addresses corresponding to a Burst-TLB-granule-size, wherein the Burst-TLB-granule-size is based on the integer M and on an address range corresponding to the burst entry tag,
wherein determining whether the comparand matches the burst entry tag comprises determining whether the comparand matches the corresponding burst entry tag of at least one of the burst entries,
the method further comprising:
upon determining that none of the burst entry tags matches the comparand, detecting a miss;
upon detecting the miss, generating an updated burst entry, the updated burst entry including address translation for an address range that includes the comparand, generating the updated burst entry comprising:
receiving a page of Stage-1 mapping information, the page of Stage-1 mapping information having a Stage-1 page size,
receiving a page of Stage-2 mapping information, the page of Stage-2 mapping information having a Stage-2 page size,
determining an effective page size, the effective page size being a minimum from among the Stage-1 page size and the Stage-2 page size,
setting a translation size, as
translation size=max(Effective Page size,2 Q ×Burst-TLB-granule-size),

where Q=Log base 2 of M, and

generating the updated burst entry based on the translation size and on mapping information from the page of Stage-1 mapping information and the page of Stage-2 mapping information; and

storing the updated burst entry as one of the plurality of burst entries.

13. The method of claim 12 , further comprising, in association with determining an effective page size,
setting an invalidation size, as
invalidation size=max(Invalidation Page size,2 Q ×Burst-TLB-granule-size),

the Invalidation page size being the Stage-1 page size.

14. The method of claim 13 , wherein storing the updated burst entry is based, at least in part, on a relative size of the effective page size and M times the Burst TLB granule size.

15. The method of claim 14 , wherein upon the effective page size being greater than 2 Q times the burst TLB granule size, storing the updated burst entry comprises setting same translation data in all M of the translation data units.

16. The method of claim 12 , wherein generating the updated burst entry comprises discarding mapping information from the page of Stage-1 mapping information, or mapping information from the page of Stage-2 mapping information, or both, that are outside of a block of interest, and the updated burst entry being mapping information from the page of Stage-1 mapping information, or mapping information from the page of Stage-2 mapping information, or both, within the block of interest.

17. The method of claim 1 , wherein the virtual address comprises one or more selection bits, wherein selecting the candidate

Assignees

• Qualcomm Inc

Inventors

• Podaima Jason Edward
• Wiercienski Paul Christopher John
• Miretsky Alexander

Classifications

• G06F2212/1041

  Resource optimization · CPC title

• G06F2212/654

  Look-ahead translation · CPC title

• G06F2212/651

  Multi-level translation tables · CPC title

• G06F2212/683

  Invalidation · CPC title

• G06F12/1036 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title