VPA with integrated object recognition and facial expression recognition
US-12282606-B2 · Apr 22, 2025 · US
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Mark William patents
Mark William is listed as an inventor on 24 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Mark William |
| Total patents | 24 |
| First publication | May 14, 2015 |
| Latest publication | Apr 22, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Configurable and programmable image processor unit
US-11250537-B2 · Feb 15, 2022 · US
Vpa with integrated object recognition and facial expression recognition
US-2021081056-A1 · Mar 18, 2021 · US
VPA with integrated object recognition and facial expression recognition
US-10884503-B2 · Jan 5, 2021 · US
Determination of per line buffer unit memory allocation
US-10685423-B2 · Jun 16, 2020 · US
Configurable and programmable image processor unit
US-2020167890-A1 · May 28, 2020 · US
Determination of per line buffer unit memory allocation
US-2020098083-A1 · Mar 26, 2020 · US
Macro I/O unit for image processor
US-10504480-B2 · Dec 10, 2019 · US
Configurable and programmable image processor unit
US-10489878-B2 · Nov 26, 2019 · US
Determination of per line buffer unit memory allocation
US-10430919-B2 · Oct 1, 2019 · US
Recent patents
Latest publications not already listed above.
Architecture for high performance, power efficient, programmable image processing
US-10417732-B2 · Sep 17, 2019 · US
Macro I/O unit for image processor
US-10380969-B2 · Aug 13, 2019 · US
Pharmaceutical suspension composition
US-10238640-B2 · Mar 26, 2019 · US
Determination of per line buffer unit memory allocation
US-2018330467-A1 · Nov 15, 2018 · US
Configurable and programmable image processor unit
US-2018330466-A1 · Nov 15, 2018 · US
Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US-9978116-B2 · May 22, 2018 · US
Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and a Two-Dimensional Shift Register
US-2018005347-A1 · Jan 4, 2018 · US
Architecture for high performance, power efficient, programmable image processing
US-2017256021-A1 · Sep 7, 2017 · US
Macro I/O Unit for Image Processor
US-2017256230-A1 · Sep 7, 2017 · US
Macro I/O Unit for Image Processor
US-2017249921-A1 · Aug 31, 2017 · US
Vpa with integrated object recognition and facial expression recognition
US-2017160813-A1 · Jun 8, 2017 · US
Pharmaceutical Suspension Composition
US-2017065567-A1 · Mar 9, 2017 · US
Enriched financial transaction records
US-2015242961-A1 · Aug 27, 2015 · US
Financial conversation management systems and methods
US-2015134449-A1 · May 14, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Google Llc | 10 |
| Stanford Res Inst Int | 6 |
| Google Inc | 6 |
| Wyeth Llc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06T1/20 | 16 |
| G06T1/60 | 10 |
| G06V40/20 | 8 |
| G06V40/16 | 8 |
| G06K9/00335 | 7 |