Macro I/O unit for image processor

Patent metadata

Field	Value
Publication number	US-10504480-B2
Application number	US-201715599086-A
Country	US
Kind code	B2
Filing date	May 18, 2017
Priority date	Feb 28, 2016
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.

First claim

What is claimed is:

1. A device comprising:
one or more processors; and
a plurality of channel units that are each configured to implement a separate respective channel of data transfer to an external memory,
wherein each channel unit comprises formatting logic that is configured to receive image data from the external memory in a first format and convert the image data into a second format, and
wherein each channel unit comprises addressing logic that is configured to determine an order in which image data should be read from the external memory,
wherein the plurality of channel units comprises a pair of the channel units that are configured to implement separate respective channels of data transfer to the external memory and to implement ad hoc reading of non-sequential regions of image data from the external memory,
wherein a first channel unit of the pair of channel units is configured to receive coordinate values generated by a processor of the one or more processors, the coordinate values identifying a location within the image data, and wherein the first channel unit is configured to forward the coordinate values to a second channel unit of the pair of channel units,
wherein the second channel unit of the pair of channel units is configured to receive the coordinate values forwarded from the first channel unit of the pair of channel units, to use
the addressing logic to request, from the external memory, a region of image data having a location identified by the coordinate values generated by the processor, the region being a portion of a first row of the image data that is less than all of the first row of a full frame of image data stored in the external memory, to use the reformatting logic to reformat the region of image data, and to forward the reformatted region of image data for access by the processor that generated the coordinate values.

2. The device of claim 1 , wherein the addressing logic is configured to access a programmable context register space that is configured to store data representing a size of the region of image data that the second channel unit should read from the external memory.

3. The device of claim 1 , wherein the addressing logic for the second channel unit causes the second channel unit to read, from the region of image data all rows from the region of image data before reading data from outside the region of image data.

4. The device of claim 1 , wherein the device comprises a line buffer that is configured to store image data received from the one or more channel units, and wherein a size of the region of image data requested by the second channel unit is based on a size of data processed by the line buffer.

5. The device of claim 1 , wherein the formatting logic is configured to convert pixel values encoding multiple channels into respective separate image regions for the multiple channels.

6. The device of claim 1 , wherein the second channel unit is configured to determine addresses for the region of image data from the coordinates received from the first channel unit and from a size of the region of image data determined from a programmable context register space of the second channel unit.

7. A method comprising:
receiving, by a first channel unit of the pair of channel units of a device, coordinate values generated by a processor of the device, the coordinate values identifying a location within image data stored in an external memory of the device, wherein the device comprises a pair of the channel units that are configured to implement separate respective channels of data transfer to the external memory and to implement ad hoc reading of non-sequential regions of image data from the external memory;
forwarding, by the first channel unit, the coordinate values to a second channel unit of the pair of channel units;
receiving, by the second channel unit, the coordinate values forwarded from the first channel unit of the pair of channel units;
using, by the second channel unit using addressing logic to request, from the external memory, a region of image data having a location identified by the coordinate values generated by the processor, the region being a portion of a first row of a full frame of image data that is less than all of the first row of a full frame of image data stored in the external memory;
receiving, by formatting logic of the second channel unit, a region of image data from the requested portion of the first row, the region of image data from the requested portion of the first row being in a first format;
converting, by the formatting logic of the second channel unit, the region of image data from the requested portion of the first row from a first format to a second format; and
providing, by the second channel unit to the processor that generated the coordinate value, the reformatted region of image data from the requested portion of the first row in the second format.

8. The method of claim 7 , further comprising:
after requesting a first row of the region of image data, requesting, by the second channel unit according to an order determined by the addressing logic, data from a second row of region of image data, the requested portion of the second row being less than all of the second row of image data.

9. The method of claim 7 , further comprising determining, by the addressing logic, an order in which rows of the region of image data should be read from the external memory including accessing, by the addressing logic of the second channel unit, a programmable context register space storing data representing an order in which rows of the region of image data should be read from the external memory.

10. The method of claim 7 , wherein the order determined by the addressing logic for the second channel unit specifies requesting, from the region of image data all rows from the region of image data before reading data from outside the region of image data.

11. The method of claim 7 , wherein the device comprises a line buffer that is configured to store image data received from the one or more channel units, and further comprising:
determining a size of the region of image data to be requested by the second channel unit based on a size of data processed by the line buffer.

12. The method of claim 7 , wherein converting, by the formatting logic, the image data from the first format to the second format comprises converting, by the formatting logic, pixel values encoding multiple channels into respective separate image regions for the multiple channels.

13. The method of claim 7 , further comprising determining, by the second channel unit, addresses for the region of image data from the coordinates received from the first channel unit and from a size of the region of image data determined from a programmable context register space of the second channel unit.

Assignees

• Google Llc

Inventors

• Meixner Albert
• Desai Neeti
• Manatunga Dilan
• Redgrave Jason Rupert
• Mark William

Classifications

• G06T1/60

  Memory management · CPC title

• G06F15/17

  using an input/output type connection, e.g. channel, I/O port · CPC title

• G09G5/02

  characterised by the way in which colour is displayed {(details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607)} · CPC title

• H04N2201/3291

  of less than a complete line of data · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title