Input/output (I/O) store protocol for pipelining coherent operations
US-12332783-B2 · Jun 17, 2025 · US
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Lopes Kevin patents
Lopes Kevin is listed as an inventor on 8 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Lopes Kevin |
| Total patents | 8 |
| First publication | Sep 10, 2020 |
| Latest publication | Jun 17, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Input/output (i/o) store protocol for pipelining coherent operations
US-2024119000-A1 · Apr 11, 2024 · US
Coherency maintenance via physical cache coordinate comparison
US-11099989-B2 · Aug 24, 2021 · US
Multilevel cache eviction management
US-10915461-B2 · Feb 9, 2021 · US
Page-based memory operation with hardware initiated secure storage key update
US-10891232-B2 · Jan 12, 2021 · US
Page-based memory operation with hardware initiated secure storage key update
US-2020301832-A1 · Sep 24, 2020 · US
Coherency maintenance via physical cache coordinate comparison
US-2020293448-A1 · Sep 17, 2020 · US
Multilevel cache eviction management
US-2020285592-A1 · Sep 10, 2020 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 8 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F2212/1024 | 4 |
| G06F12/0811 | 4 |
| G06F12/084 | 4 |
| G06F12/0828 | 2 |
| G06F12/0875 | 2 |