Multilevel cache eviction management

Patent metadata

Field	Value
Publication number	US-10915461-B2
Application number	US-201916292762-A
Country	US
Kind code	B2
Filing date	Mar 5, 2019
Priority date	Mar 5, 2019
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.

First claim

What is claimed is:

1. A computer-implemented method for cache eviction, the method comprising:
detecting first data in a shared cache and the same first data in a first cache in response to a request by a first processor,
determining that the first data and the same first data have a mid-level cache eviction priority at the first cache and the shared cache, wherein determining that the first data has a mid-level cache eviction priority is based on the presence of an early eviction bit, and wherein the presence of the early eviction bit is based in part on an estimated time the first processor operates on the first data;
detecting a request from a second processor for the same first data as requested by the first processor;
determining that the second processor requires the first data for a longer period of time than the estimated time the first processor operates on the first data;
loading duplicated first data to a second cache, wherein the duplicated data has a low-level cache eviction priority at the second cache; and
removing the early eviction bit of the first data at the shared cache.

2. The computer-implemented method of claim 1 , wherein the shared cache is level 4 (L4) cache.

3. The computer-implemented method of claim 1 , wherein first cache and the second cache are each a respective level 3 (L3) cache.

4. The computer-implemented method of claim 1 , wherein determining that the second processor requires the first data for a longer period of time than the estimated time the first processor operates on the first data is based in part on the absence of an early eviction bit in the request for data from the second processor.

5. The computer-implemented method of claim 1 , wherein the first cache and the shared cache are managed under a least recently used (LRU) algorithm.

6. A system for cache eviction, the system comprising:
a processor communicatively coupled to a memory, the processor configured to:
detect a first data in a shared cache and a same first data in a first cache in response to a request by a first processor,
determine that the first data and the same first data have a mid-level cache eviction priority at the first cache and the shared cache, wherein determining that the first data has a mid-level cache eviction priority is based on the presence of an early eviction bit, and wherein the presence of the early eviction bit is based in part on an estimated time the first processor operates on the first data;
detect a request from a second processor for a same first data as requested by the first processor;
determine that the second processor requires the first data for a longer period of time than the estimated time the first processor operates on the first data;
load duplicated first data to a second cache, wherein the duplicated data has a low-level cache eviction priority at the second cache; and
remove the early eviction bit of the first data at the shared cache.

7. The system of claim 6 , wherein the shared cache is a level 4 (L4) cache.

8. The system of claim 6 , wherein first cache and the second cache are each a respective level 3 (L3) cache.

9. The system of claim 6 , wherein determining that the second processor has requires the first data for a longer period of time than the estimated time the first processor operates on the first data is based in part on the absence of an early eviction bit in the request for data from the second processor.

10. The system of claim 6 , wherein the first cache and the shared cache are managed under a least recently used (LRU) algorithm.

11. A computer program product for cache eviction, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the instructions executable by a processor to cause the processor to:
detect first data in a shared cache and the same first data in a first cache in response to a request by a first processor,
determine that the first data and the same first data have a mid-level cache eviction priority at the first cache and the shared cache, wherein determining that the first data has a mid-level cache eviction priority is based on the presence of an early eviction bit, and wherein the presence of the early eviction bit is based in part on an estimated time the first processor operates on data;
detect a request from a second processor for the same first data requested by the first processor;
determine that the second processor requires the first data for a longer period of time than the estimated time the first processor operates on the first data;
load duplicated first data to a second cache, wherein the duplicated first data has a low-level cache eviction priority at the second cache; and
remove the early eviction bit of the first data at the shared cache.

12. The computer program product of claim 11 , wherein the shared cache is a level 4 (L4) cache.

13. The computer program product of claim 11 , wherein first cache and the second cache are each a respective level 3 (L3) cache.

14. The computer program product of claim 11 , wherein determining that the second processor requires the first data for a longer period of time than the estimated time the first processor operates on the first data is based in part of the absence on an early eviction bit in the request for data from the second processor.

Assignees

• IBM

Inventors

• Ambroladze Ekaterina M
• Sonnelitter Iii Robert J
• Klein Matthias
• Walters Craig
• Lopes Kevin
• Blake Michael A
• Bronson Tim
• Klapproth Kenneth
• Papazova Vesselina
• Huynh Hieu T

Classifications

• G06F12/126 Primary

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/128 Primary

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title

• G06F12/084

  with a shared cache · CPC title