Page-based memory operation with hardware initiated secure storage key update

Patent metadata

Field	Value
Publication number	US-10891232-B2
Application number	US-201916360468-A
Country	US
Kind code	B2
Filing date	Mar 21, 2019
Priority date	Mar 21, 2019
Publication date	Jan 12, 2021
Grant date	Jan 12, 2021

Abstract

Methods and systems for secure storage protection for memory operations are provided. Aspects include providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors, wherein each of the plurality of clusters share a first cache memory, providing a cluster shared cache integrated circuit to manage a second cache memory shared among the plurality of clusters, providing a system memory associated with each of the plurality of clusters, receiving, by a memory controller, a memory operation request from one of the plurality of processors, wherein the memory operation includes a store command, and wherein the memory controller is configured to perform the memory operation and atomically write a secure storage key for the memory operation with the store command of the memory operation.

First claim

What is claimed is:

1. A computer-implemented method comprising:
providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors, wherein each of the plurality of clusters shares a first cache memory;
providing a cluster shared cache integrated circuit to manage a second cache memory shared among the plurality of clusters;
providing a system memory associated with each of the plurality of clusters; and
receiving, by a memory controller, a memory operation request from one of the plurality of processors, wherein the memory operation includes a store command;
wherein the memory controller is configured to:
perform the memory operation; and
atomically write a secure storage key for the memory operation with the store command of the memory operation, wherein the memory operation includes a move page command;

generating, by a hardware engine, the secure storage key for the move page command; and
sending, to the memory controller, the secure storage key along with a destination page address for the move page command.

2. The computer-implemented method of claim 1 , wherein performing the memory operation and writing the secure storage key comprise:
defining, by the memory controller, a memory command comprising the memory operation and the write secure storage key.

3. The computer-implemented method of claim 1 , wherein the memory operation is associated with the system memory.

4. The computer-implemented method of claim 1 , wherein the memory operation includes a store pad command.

5. The computer-implemented method of claim 4 , further comprising:
generating, by a hardware engine, a secure storage key for the store pad command; and
sending, to the memory controller, the secure storage key along with a target page address for the store pad command.

6. The computer-implemented method of claim 1 , further comprising performing a storage validity check in the system memory for the memory operation.

7. The computer-implemented method of claim 1 , further comprising performing a secure storage protection check for the memory operation.

8. The computer-implemented method of claim 7 , further comprising overriding the secure storage protection check by supplying a generic key.

9. A system for secure storage protection for memory operations, the system comprising:
a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors, wherein each of the plurality of clusters shares a first cache memory;
a cluster shared cache integrated circuit to manage a second cache memory shared among the plurality of clusters;
a system memory associated with each of the plurality of clusters; and
a memory controller configured to:
receive a memory operation request from one of the plurality of processors, wherein the memory operation includes a store command;
perform the memory operation; and
atomically write a secure storage key for the memory operation with the store command of the memory operation, wherein the memory operation includes a move page command;

generating, by a hardware engine, the secure storage key for the move page command; and
sending, by the hardware engine to the memory controller, the secure storage key along with a destination page address for the move page command.

10. The system of claim 9 , wherein performing the memory operation and writing the secure storage key comprise:
defining, by the memory controller, a memory command comprising the memory operation and the write secure storage key.

11. The system of claim 9 , wherein the memory operation is associated with the system memory.

12. The system of claim 9 , wherein the memory operation includes a store pad command.

13. A computer program product for secure storage protection for memory operations comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a memory controller to cause the memory controller to perform a method comprising:
receiving a memory operation request from one of a plurality of processors, wherein the memory operation includes a store command;
performing the memory operation; and
atomically writing a secure storage key for the memory operation with the store command of the memory operation, wherein the memory operation includes a move page command;
generating, by a hardware engine, the secure storage key for the move page command; and
sending, to a memory controller, the secure storage key along with a destination page address for the move page command.

14. The computer program product of claim 13 , wherein performing the memory operation and writing the secure storage key comprise:
defining, by the memory controller, a memory command comprising the memory operation and the write secure storage key.

15. The computer program product of claim 13 , wherein the memory operation is associated with a system memory.

Assignees

• IBM

Inventors

• Lopes Kevin
• Berger Deanna P D
• Kohl Jason D
• Sonnelitter Iii Robert J

Classifications

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F2212/622

  State-only directory, i.e. not recording identity of sharing or owning nodes · CPC title

• G06F3/062

  Securing storage systems · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F12/084 Primary

  with a shared cache · CPC title