SIMD operand permutation with selection from among multiple registers
US-12008377-B2 · Jun 11, 2024 · US
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Kenney Robert D patents
Kenney Robert D is listed as an inventor on 28 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kenney Robert D |
| Total patents | 28 |
| First publication | Feb 25, 2016 |
| Latest publication | Jun 11, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
SIMD Operand Permutation with Selection from among Multiple Registers
US-2023325196-A1 · Oct 12, 2023 · US
SIMD operand permutation with selection from among multiple registers
US-11645084-B2 · May 9, 2023 · US
Multi-channel data path circuitry
US-11422822-B2 · Aug 23, 2022 · US
Routing circuitry for permutation of single-instruction multiple-data operands
US-11294672-B2 · Apr 5, 2022 · US
Datapath circuitry for math operations using SIMD pipelines
US-11256518-B2 · Feb 22, 2022 · US
SIMD Operand Permutation with Selection from among Multiple Registers
US-2021406031-A1 · Dec 30, 2021 · US
Multi-channel Data Path Circuitry
US-2021349725-A1 · Nov 11, 2021 · US
SIMD operand permutation with selection from among multiple registers
US-11126439-B2 · Sep 21, 2021 · US
Register file arbitration
US-11080055-B2 · Aug 3, 2021 · US
Recent patents
Latest publications not already listed above.
SIMD Operand Permutation with Selection from among Multiple Registers
US-2021149679-A1 · May 20, 2021 · US
Datapath Circuitry for Math Operations using SIMD Pipelines
US-2021109761-A1 · Apr 15, 2021 · US
Routing Circuitry for Permutation of Single-Instruction Multiple-Data Operands
US-2021055931-A1 · Feb 25, 2021 · US
Register File Arbitration
US-2021055929-A1 · Feb 25, 2021 · US
GPU task scheduling
US-10902545-B2 · Jan 26, 2021 · US
Data alignment and formatting for graphics processing unit
US-10769746-B2 · Sep 8, 2020 · US
Techniques for ALU sharing between threads
US-10699366-B1 · Jun 30, 2020 · US
Pipelined allocation for operand cache
US-10678548-B2 · Jun 9, 2020 · US
Pipelined Allocation for Operand Cache
US-2020065104-A1 · Feb 27, 2020 · US
Hints for shared store pipeline and multi-rate targets
US-10452401-B2 · Oct 22, 2019 · US
Power saving with dynamic pulse insertion
US-10270434-B2 · Apr 23, 2019 · US
Pessimistic dependency handling based on storage regions
US-10114650-B2 · Oct 30, 2018 · US
Hints for Shared Store Pipeline and Multi-Rate Targets
US-2018267804-A1 · Sep 20, 2018 · US
Pipeline dependency resolution
US-9519944-B2 · Dec 13, 2016 · US
Pessimistic dependency handling
US-2016246598-A1 · Aug 25, 2016 · US
Data alignment and formatting for graphics processing unit
US-2016093014-A1 · Mar 31, 2016 · US
Pipeline dependency resolution
US-2016063662-A1 · Mar 3, 2016 · US
Gpu task scheduling
US-2016055610-A1 · Feb 25, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Apple Inc | 28 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/3851 | 15 |
| G06F9/3887 | 15 |
| G06T1/20 | 15 |
| G06F9/3828 | 10 |
| G06F9/3888 | 9 |