Data alignment and formatting for graphics processing unit

Patent metadata

Field	Value
Publication number	US-10769746-B2
Application number	US-201414496934-A
Country	US
Kind code	B2
Filing date	Sep 25, 2014
Priority date	Sep 25, 2014
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A data queuing and format apparatus is disclosed. A first selection circuit may be configured to selectively couple a first subset of data to a first plurality of data lines dependent upon control information, and a second selection circuit may be configured to selectively couple a second subset of data to a second plurality of data lines dependent upon the control information. A storage array may include multiple storage units, and each storage unit may be configured to receive data from one or more data lines of either the first or second plurality of data lines dependent upon the control information.

First claim

What is claimed is:

1. An apparatus, comprising:
a first selection circuit configured to selectively couple data bits of a first subset of a plurality of data bits conveyed on a bus to respective data lines of a first plurality of data lines, the first plurality of data lines being column data lines;
a second selection circuit configured to selectively couple data bits of a second subset of the plurality of data bits conveyed on the bus to a respective data line of a second plurality of data lines, the second plurality of data lines being row data lines;
a first storage array including a plurality of storage units, wherein each storage unit of the plurality of storage units is configured to selectively receive data from at least one data line of the first plurality of data lines or at least one data line of the second plurality of data lines such that various bit positions of the data bits of the first and second subsets are selectively stored in different relative positions within the first storage array; and
a second storage array configured to store control information separately from data stored in the first storage array, wherein the first and second selection circuits are coupled to receive control information from the second storage array;
wherein each of the first and second selection circuits is configured to store data to conform to a data format employed by a destination of the data.

2. The apparatus of claim 1 , wherein the first selection circuit includes a plurality of multiplex circuits, wherein each multiplex circuit is configured to selectively couple a given data bit of the plurality of data bits to a respective data line of the first plurality of data lines.

3. The apparatus of claim 1 , wherein the second selection circuits includes a plurality of multiplex circuits, wherein each multiplex circuit is configured to selectively coupled a given data bit of the plurality of data bits to a respective data line of the second plurality of data lines.

4. The apparatus of claim 1 , wherein each storage unit of the plurality of storage units includes one or more multiplex circuits, wherein each multiplex circuit is configured to receive data from a given data line of the first plurality of data lines or a given data line of a second plurality of data lines.

5. The apparatus of claim 1 , wherein the first selection circuit is configured to selectively couple the data bits of the first subset of the plurality of data bits to the respective data lines of a first plurality of data lines dependent upon at least a first portion of the control information, and wherein the second selection circuit is configured to selectively couple the data bits of the second subset of the plurality of data bits to the respective data lines of the second plurality of data lines dependent upon at least a second portion of the control information.

6. A method, comprising:
receiving control information and data from a memory, wherein the data includes a plurality of data bits;
storing the control information in a first queue;
providing the control information to selection circuits;
selecting, using the selection circuits, a subset of the plurality of data bits dependent upon a portion of the control information, wherein selecting includes a first selection circuit selectively coupling data bits of a first subset of the plurality of data bits from a bus to column data lines in a second queue and a second selection circuit selectively coupling a second subset of the plurality of data bits from the bus to row data lines in the second queue, such that various bit positions of the data bits of the first and second subsets are selectively stored in different relative positions within the second queue; and
storing the subset of the plurality of data bits into the second queue, the second queue being separate from the first queue, wherein storing the subset of the plurality of data bits further comprise storing the plurality of data bits to conform to a data format employed by a destination of the plurality of data bits.

7. The method of claim 6 , wherein the second queue includes a plurality of data storage units, wherein each data storage unit is coupled to at least one data line of a first plurality of data lines, and at least one data line of a second plurality of data lines.

8. The method of claim 7 , wherein a given data line of the first plurality of data lines is orthogonal to a respective data line of the second plurality of data lines.

9. The method of claim 7 , wherein storing the subset of the plurality of data bits comprises storing one or more data bits of the subset of the plurality of data bits in a given one of the plurality of data storage units.

10. The method of claim 9 , wherein storing the one or more data bits of the subset of the plurality of data bits in the given one of the plurality of data storage units comprises selectively receiving data from either the at least one data line of the first plurality of data lines or the at least one data line of the second plurality of data lines.

11. The method of claim 6 , wherein storing the control information comprises decoding the control information.

12. The method of claim 6 , further comprising sending at least a portion of the stored subset of the plurality of data bits to at least one register.

13. A system, comprising:
a memory; and
a graphics unit including a first functional unit and a second functional unit, wherein the graphics unit is configured to:
receive control information and data from the memory, the data including a plurality of data bits;
store the control information in a first queue;
provide the control information to selection circuits;
select, using the selection circuits, a portion of the data dependent upon a portion of the control information provided from a first queue; and
store the portion of the data in a second queue separate from the first queue, wherein the second queue includes a plurality of storage units, and wherein each storage unit of the plurality of storage units is coupled to at least one data line of a first plurality of data lines and at least one data line of a second plurality of data lines, the first plurality of data lines being column data lines and the second plurality of data lines being row data lines;
wherein selecting a portion of the data includes a first one of the selection circuits selectively coupling data bits of a first subset of the plurality of data bits from a bus to column data lines in the second queue and a second selection circuit selectively coupling a second subset of the plurality of data bits from the bus to row data lines in the second queue such that various bit positions of the data bits of the portion are selectively stored in different relative positions within the second queue; and
wherein storing the portion of the data includes storing the data in a data format conforming to a destination of the portion of data.

14. The system of claim 13 , wherein to store the portion of the data in the second queue, the graphics unit is further configured to store the portion of the data into a subset of a plurality of storage units in the second queue dependent upon the control information.

15. The system of claim 13 , wherein the portion of the data includes a plurality of data bits, and wherein to store the portion of the data in the second queue, the graphics unit is further configured to store a subset of the plurality of data bits into a given one of a plurality of storage unit in the second queue.

16. The system of claim 15 , wherein to store the subset of the plurality of

Assignees

• Apple Inc

Inventors

• Xia Liang
• Kenney Robert D
• Goodman Benjiman L
• Potter Terence M

Classifications

• G06F9/00

  Arrangements for program control, e.g. control units (program control for peripheral devices G06F13/10) · CPC title

• G06F9/3012

  Organisation of register space, e.g. banked or distributed register file · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T1/60

  Memory management · CPC title