Pipelined allocation for operand cache

Patent metadata

Field	Value
Publication number	US-10678548-B2
Application number	US-201816112614-A
Country	US
Kind code	B2
Filing date	Aug 24, 2018
Priority date	Aug 24, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

Techniques are disclosed relating to controlling an operand cache in a pipelined fashion. An operand cache may cache operands fetched from the register file or generated by previous instructions to improve performance and/or reduce power consumption. In some embodiments, instructions are pipelined and separate tag information is maintained to indicate allocation of an operand cache entry and ownership of the operand cache entry. In some embodiments, this may allow an operand to remain in the operand cache (and potentially be retrieved or modified) during an interval between allocation of the entry for another operand and ownership of the entry by the other operand. This may improve operand cache efficiency by allowing the entry to be used while to retrieving the other operand from the register file, for example.

First claim

What is claimed is:

1. An apparatus, comprising:
a register file configured to store operands;
an operand cache comprising a plurality of entries each configured to store one or more operands, wherein the apparatus is configured to fetch input operands from the register file for storage in the operand cache;
execution circuitry configured to perform operations on operands stored in entries in the operand cache; and
pipeline circuitry configured to process instructions for execution, including:
first tag circuitry configured to indicate allocation of an entry for a first operand; and
second tag circuitry configured to indicate ownership of the entry for the first operand;
wherein, during a time interval between allocation and ownership of the entry for the first operand, the apparatus is configured to provide a second operand from the entry as an execution input to the execution circuitry.

2. The apparatus of claim 1 , wherein the apparatus is configured to use the first tag circuitry to determine:
whether operands are hit in the operand cache; and
which entry to evict from the operand cache.

3. The apparatus of claim 1 , wherein the apparatus is configured to use the second tag circuitry when reading data from the operand cache.

4. The apparatus of claim 1 , further comprising:
one or more storage elements configured to store operand data in order for operands evicted from the operand cache until the evicted operand data is written to the register file.

5. The apparatus of claim 4 , wherein the one or more storage elements are configured to forward data to the operand cache in response to a hit for a corresponding operand stored in the one or more storage elements.

6. The apparatus of claim 1 , wherein the apparatus is configured to fetch data for the first operand from the register file after allocation of the entry for the first operand and prior to ownership of the entry for the first operand.

7. The apparatus of claim 1 , wherein tag data for a given entry in the operand cache includes a register address and an identifier of a group of commonly-controlled threads that specify the register address.

8. A method, comprising:
storing operands in respective entries of a register file;
storing operands in an operand cache comprising a plurality of entries each configured to store one or more operands, wherein at least a portion of the operands stored in the operand cache are fetched from the register file;
performing, by execution circuitry, operations using operands stored in entries in the operand cache; and
processing instructions prior to dispatching the instructions to the execution circuitry, including:
allocating an entry in the operand cache for a first operand from the register file;
during a time interval between allocation of the entry for the first operand and storing the first operand in the entry, maintaining information indicating ownership of the entry for a second operand;
providing the second operand as an execution input during the time interval; and
modifying the information, upon storing the first operand in the entry, to indicate ownership of the entry for the first operand.

9. The method of claim 8 , further comprising using first tag information indicating allocation of the operand to determine whether operands are hit in the operand cache and which entry to evict from the operand cache.

10. The method of claim 8 , further comprising using second tag information indicating ownership of the entry for the first operand to access the first operand for transmittal to the execution circuitry.

11. The method of claim 8 , further comprising storing operand data in order in one or more storage elements, for operands evicted from the operand cache, until the evicted operand data is written to the register file.

12. The method of claim 11 , further comprising forwarding data to the operand cache in response to a hit for a corresponding operand stored in the one or more storage elements.

13. The method of claim 8 , further comprising fetching data for the first operand from the register file after allocation of the entry for the first operand and prior to ownership of the entry for the first operand.

14. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, including:
a register file configured to store operands;
an operand cache comprising a plurality of entries each configured to store one or more operands, wherein the circuit is configured to fetch input operands from the register file for storage in the operand cache;
execution circuitry configured to perform operations on operands stored in entries in the operand cache; and
pipeline circuitry configured to process instructions for execution, including:
first tag circuitry configured to indicate allocation of an entry for a first operand; and
second tag circuitry configured to indicate ownership of the entry for the first operand;
wherein, during a time interval between allocation and ownership of the entry for the first operand, the circuit is configured to provide a second operand from the entry as an execution input to the execution circuitry.

15. The non-transitory computer readable storage medium of claim 14 , wherein the circuit is configured to use the first tag circuitry to determine:
whether operands are hit in the operand cache; and
which entry to evict from the operand cache.

16. The non-transitory computer readable storage medium of claim 14 , wherein the circuit is configured to use the second tag circuitry when reading data from the operand cache.

17. The non-transitory computer readable storage medium of claim 14 , wherein the circuit further includes:
one or more storage elements configured to store operand data in order for operands evicted from the operand cache until the evicted operand data is written to the register file.

18. The non-transitory computer readable storage medium of claim 17 , wherein the one or more storage elements are configured to forward data to the operand cache in response to a hit for a corresponding operand stored in the one or more storage elements.

19. The non-transitory computer readable storage medium of claim 14 , wherein the circuit is configured to fetch data for the first operand from the register file after allocation of the entry for the first operand and prior to ownership of the entry for the first operand.

20. The non-transitory computer readable storage medium of claim 14 , wherein tag data for a given entry in the operand cache includes a register address and an identifier of a group of commonly-controlled threads that specify the register address.

Assignees

• Apple Inc

Inventors

• Kenney Robert D
• Potter Terence M
• Havlir Andrew M
• Ayinala Sivayya V

Classifications

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/3802 Primary

  Instruction prefetching · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/3832 Primary

  Value prediction for operands; operand history buffers · CPC title