Efficient delay calculations in replicated designs
US-12596861-B2 · Apr 7, 2026 · US
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Keller Igor patents
Keller Igor is listed as an inventor on 23 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Keller Igor |
| Total patents | 23 |
| First publication | Jan 20, 2015 |
| Latest publication | Apr 7, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Circuit design modification using timing-based yield calculation
US-12086529-B1 · Sep 10, 2024 · US
Efficient delay calculations in replicated designs
US-2024143877-A1 · May 2, 2024 · US
Cell instance charge model for delay calculation
US-11775719-B1 · Oct 3, 2023 · US
Method, system, and product for deferred merge based method for graph based analysis pessimism reduction
US-11188696-B1 · Nov 30, 2021 · US
Methods, systems, and computer program product for characterizing timing behavior of an electronic design with a derived current waveform
US-11023640-B1 · Jun 1, 2021 · US
Methods, systems, and computer program product for characterizing an electronic design with a susceptibility window
US-11023636-B1 · Jun 1, 2021 · US
Analyzing clock jitter using delay calculation engine
US-10963610-B1 · Mar 30, 2021 · US
Characterizing electronic component parameters including on-chip variations and moments
US-10789406-B1 · Sep 29, 2020 · US
Method and apparatus for yield calculation using statistical timing data that accounts for path and stage delay correlation
US-10430536-B1 · Oct 1, 2019 · US
Recent patents
Latest publications not already listed above.
Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design
US-10275554-B1 · Apr 30, 2019 · US
Pseudo-inverter configuration for signal electromigration analysis
US-10192012-B1 · Jan 29, 2019 · US
Systems and methods for statistical static timing analysis
US-10185795-B1 · Jan 22, 2019 · US
Systems and methods for statistical static timing analysis
US-10073934-B1 · Sep 11, 2018 · US
System and method for accurate modeling of back-miller effect in timing analysis of digital circuits
US-9928324-B1 · Mar 27, 2018 · US
Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact
US-9881123-B1 · Jan 30, 2018 · US
Methods, systems, and articles of manufacture for enhancing timing analyses with reduced timing libraries for electronic designs
US-9710593-B1 · Jul 18, 2017 · US
Using waveform propagation for accurate delay calculation
US-9582626-B1 · Feb 28, 2017 · US
View data sharing for efficient multi-mode multi-corner timing analysis
US-9384310-B1 · Jul 5, 2016 · US
Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages
US-9129078-B1 · Sep 8, 2015 · US
Lumped aggressor model for signal integrity timing analysis
US-9003342-B1 · Apr 7, 2015 · US
Static timing analysis methods for integrated circuit designs using a multi-CCC current source model
US-8966421-B1 · Feb 24, 2015 · US
Method and apparatus for comprehension of common path pessimism during timing model extraction
US-8938703-B1 · Jan 20, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Cadence Design Systems Inc | 23 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F30/3312 | 18 |
| G06F2119/12 | 17 |
| G06F30/367 | 11 |
| G06F30/3315 | 8 |
| G06F17/5031 | 7 |