Methods, systems, and articles of manufacture for enhancing timing analyses with reduced timing libraries for electronic designs

Patent metadata

Field	Value
Publication number	US-9710593-B1
Application number	US-201514883482-A
Country	US
Kind code	B1
Filing date	Oct 14, 2015
Priority date	Oct 14, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Disclosed are techniques for enhancing timing analyses with reduced timing libraries for electronic designs. These techniques determine dominance relations for multiple timing models for timing analyses and generate a dominance adjacency data structure based at least in part upon the dominance relations. The dominance adjacency data structure may be stored at a first location of a non-transitory computer accessible storage medium. The plurality of timing models may be reduced into a reduced set of timing models at least by providing the dominance adjacency data structure as an input to a transformation and further by transforming the dominance adjacency data structure with the transformation into the reduced set of timing models that are used in timing analyses for an electronic design or a portion thereof.

First claim

We claim:

1. A computer implemented method for enhancing timing analyses with reduced timing libraries for electronic designs, comprising:
determining dominance relations for a plurality of timing models based in part or in whole upon one or more waveform-based criteria generated with a plurality of waveforms for performing one or more timing analyses on an electronic design or a portion thereof;
generating and storing a dominance adjacency data structure at a first location in a non-transitory computer accessible storage medium based in part or in whole the dominance relations;
reducing, at a transform module that is stored at least partially in memory and coupled with a micro-processor of a computing system, the plurality of timing models into a reduced set of timing models at least by providing the dominance adjacency data structure as an input to a transformation and by transforming the dominance adjacency data structure with the transformation into the reduced set of timing models; and
implementing the electronic design or the portion thereof based in part or in whole upon results of the one or more timing analyses with at least the reduced set of timing models.

2. The computer implemented method of claim 1 , further comprising:
identifying the plurality of timing models from characterization results of the electronic design or the portion thereof having a plurality of inputs; and
generating timing analysis results at least by performing the one or more timing analyses with the reduced set of timing models.

3. The computer implemented method of claim 1 , further comprising:
identifying a plurality of data structures from the plurality of timing models; and
generating a first matrix based in part or in whole upon the plurality of timing models.

4. The computer implemented method of claim 3 , wherein a timing model of the plurality of timing models includes an output waveform data structure including output waveform data for the electronic design or the portion thereof.

5. The computer implemented method of claim 3 , further comprising:
setting diagonal entries of the first matrix to a first value indicative of self-dominance of the plurality of timing models; and
setting non-diagonal entries of the first matrix to the first value or a second value based in part or in whole upon the dominance relations for the plurality of timing models, the second value indicative of a first timing model not dominating a second timing model.

6. The computer implemented method of claim 5 , further comprising:
identifying a first output waveform from a first timing model and a second output waveform from a second timing model; and
aligning the first waveform with the second waveform based in part or in whole upon first delay data of the first timing model and second delay data of the second timing data.

7. The computer implemented method of claim 5 , further comprising:
identifying one or more dominance criteria based in part or in whole upon a plurality of waveforms of the plurality of timing models, rather than upon slew and/or delay data, for determining the dominance relations.

8. The computer implemented method of claim 7 , further comprising:
comparing the first timing model and the second timing model based in part or in whole upon the one or more dominance criteria; and
generating the dominance relations based in part or in whole upon results of comparing the first and second timing models.

9. The computer implemented method of claim 8 , further comprising:
identifying a tolerance value; and
comparing the first timing model and the second timing model based further in part upon the tolerance value.

10. The computer implemented method of claim 1 , further comprising:
receiving or generating a directed graph based in part or in whole upon the dominance adjacency data structure; and
identifying and storing a plurality of strongly connected components from the directed graph at a second location of a non-transitory computer accessible storage medium based in part or in whole upon unique indices and/or low-link indices of a plurality of vertices in the directed graph.

11. The computer implemented method of claim 10 , further comprising:
generating and storing a condensation graph at a third location of a non-transitory computer accessible storage medium at least by transforming the directed graph into the condensation graph using at least the plurality of strongly connected components.

12. The computer implemented method of claim 11 , further comprising:
identifying one or more vertices having zero input valency or zero input degree in the condensation graph; and
generating the reduced set of timing models based in part or in whole upon the one or more vertices having the zero input valency or zero input degree.

13. A system for enhancing formal verification with counter acceleration for electronic designs, comprising:
one or more modules, at least one of which is stored in part or in whole in memory and comprises at least one processor including one or more processor cores executing one or more threads in a computing system;
a non-transitory computer accessible storage medium storing thereupon program code that includes a sequence of instructions that, when executed by the at least one processor, causes the at least one processor at least to:
determine dominance relations for a plurality of timing models based in part or in whole upon one or more waveform-based criteria generated with a plurality of waveforms for performing one or more timing analyses on an electronic design or a portion thereof;
generate and store a dominance adjacency data structure at a first location in a non-transitory computer accessible storage medium based in part or in whole the dominance relations;
reduce, at a transform module that is stored at least partially in memory and coupled with a micro-processor of a computing system, the plurality of timing models into a reduced set of timing models at least by providing the dominance adjacency data structure as an input to a transformation and by transforming the dominance adjacency data structure with the transformation into the reduced set of timing models; and
implementing the electronic design or the portion thereof based in part or in whole upon results of the one or more timing analyses with at least the reduced set of timing models.

14. The system of claim 11 , wherein the program code includes the sequence of instructions that, when executed by the at least one processor, further cause the at least one processor to:
receive or generate a directed graph based in part or in whole upon the dominance adjacency data structure; and
identify and store a plurality of strongly connected components from the directed graph at a second location of a non-transitory computer accessible storage medium based in part or in whole upon unique indices and/or low-link indices of a plurality of vertices in the directed graph.

15. The system of claim 14 , wherein the program code includes the sequence of instructions that, when executed by the at least one processor, further cause the at least one processor to:
generate and store a condensation graph at a third location of a non-transitory computer accessible storage medium by transforming the directed graph into the condensation graph using at least the plurality of strongly connected components.

16. The system of claim 15 , wherein the program code includes the sequence of instructions that, when executed by the at least one processor, further cause the at least one processor to:
identify one or more ve

Assignees

• Cadence Design Systems Inc

Inventors

• Keller Igor
• Chetin Mikhail
• Sun Xiaojun

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F17/5081 Primary

  Physics · mapped topic