Systems and methods for statistical static timing analysis

Patent metadata

Field	Value
Publication number	US-10073934-B1
Application number	US-201615290362-A
Country	US
Kind code	B1
Filing date	Oct 11, 2016
Priority date	Oct 11, 2016
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. This information is then accessed in other embodiments, and scaled to generate scaled timing values describing the statistical timing characteristics of a circuit element or block estimated from the skew-based values. These values may then be used for further timing analysis.

First claim

What is claimed is:

1. A computerized method for timing analysis of a circuit design, the method comprising:
determining from at least a design file associated with the circuit design, using one or more hardware processors, an input slew and an output load for a timing path of the circuit design;
accessing, using the one or more hardware processors, a first set of statistical values associated with at least a skewness value and a standard deviation value generated from a timing delay probability distribution function (PDF) of a first element of the circuit design, the timing delay PDF having an asymmetric distribution, wherein the first set of statistical values comprises a normalized skewness value which is a normalized cube-root of skewness calculated as:

γ
normalized

=

E
⁡

[

(

D
⁡

(
x
)

-
μ

)

3

]

3

Var
⁡

[

D
⁡

(
x
)

]

for the first PDF D(x), variance function Var, mean value function E, and a mean shift value μ;
scaling, using the one or more processors, the standard deviation value and the skewness value for a bound of the timing delay PDF to generate a first scaled timing delay value for the bound; and
calculating, using the one or more processors, a first timing value based on the first scaled timing delay value;
wherein the timing analysis and circuit design is provided for fabricating semiconductor devices.

2. The method of claim 1 wherein the first timing value comprises a delay sensitivity value.

3. The method of claim 2 further comprising:
accessing corresponding statistical values for a plurality of elements of the timing path;
calculating a corresponding delay sensitivity value for each element of the timing path; and
determining a path delay sensitivity for the timing path using the corresponding delay sensitivity for each element of the timing path.

4. The method of claim 3 further comprising:
determining a delay design constraint associated with the timing path;
comparing the delay design constraint with a modeled delay using the path delay sensitivity to determine compliance with the delay design constraint.

5. The method of claim 1 wherein accessing the first set of statistical values comprises accessing a table comprising sets of statistical values for associated input slew and output load operating conditions.

6. The method of claim 5 further comprising:
determining, from a second input slew and a second output load associated with a second operating condition for the timing path of the circuit design;
accessing, using the one or more hardware processors, a second set of statistical values from the table;
scaling the second set of statistical values to generate second scaled timing delay value for the first element; and
calculating a second timing value for the first element based on the second scaled timing delay value.

7. The method of claim 1 further comprising:
determining a set of multi-mode multi-corner (MMMC) views associated with the circuit design;
determining a set of input slew and output load operating pairs associated with the set of MMMC views;
for each input slew and output load operating pair of the set of input slew and output load operating pairs:
accessing a corresponding set of statistical values, each corresponding set of statistical values associated with at least a corresponding skewness value and a corresponding standard deviation value generated from a corresponding PDF; and
calculating corresponding first timing values for each set of input slew and output load operating pairs associated with the set of MMMC views.

8. The method of claim 1 wherein the first set of statistical values further comprises a normalized kurtosis value for the fourth central moment of the first PDF.

9. The method of claim 1 further comprising:
accessing a circuit design file for the circuit design stored in a memory coupled to the one or more processors, the circuit design file comprising at least a first element and a second element;
identifying the timing delay PDF as associated with the first element, wherein the first PDF is associated with a timing characteristic type;
identifying a second PDF associated with the first characteristic type for the second element;
calculating the first set of statistical values for the first PDF, the first set of statistical values comprising at least the skewness value of the first PDF;
calculating a second set of statistical values for the second PDF; and
storing the first set of statistical values and the second set of statistical values in a first data structure configured for timing analysis using the skewness value.

10. The method of claim 1
wherein the first set of statistical values further comprises a mean-shift value determined by modeling the first PDF as a Gaussian function and determining the mean-shift value as a calculated difference between a nominal mean of the Gaussian function and a mean of the first PDF.

11. The method of claim 1 wherein the first set of statistical values are generated by a Monte-Carlo sampling of the first PDF.

12. A device for timing analysis of a circuit design comprising:
memory for storing a first data structure comprising one or more sets of timing analysis values and a design file associated with the circuit; and
one or more processors configured to perform operations comprising:
determining, from the design file, a first operating condition, the first operating condition comprising an input slew and an output load for a timing path of the circuit design;
accessing a first set of statistical values from the first data structure, the first set of statistical values associated with at least a skewness value and a standa

Assignees

• Cadence Design Systems Inc

Inventors

• Keller Igor
• Ghanta Praveen
• Mishra Arun Kumar

Classifications

• G06F2111/08

  Probabilistic or stochastic CAD · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F17/5031 Primary

  Physics · mapped topic

• G06F17/5036

  Physics · mapped topic