Method, unit and circuit for implementing Boolean logic based on computing-in-memory transistor
US-12166481-B2 · Dec 10, 2024 · US
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Gu Jiani patents
Gu Jiani is listed as an inventor on 5 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Gu Jiani |
| Total patents | 5 |
| First publication | Jul 13, 2023 |
| Latest publication | Dec 10, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Full adder circuit and multi-bit full adder
US-12073192-B2 · Aug 27, 2024 · US
Communication method for multi-chip neural network algorithm based on FPGA main control
US-12019571-B1 · Jun 25, 2024 · US
Full adder circuit and multi-bit full adder
US-2024078086-A1 · Mar 7, 2024 · US
Method, unit and circuit for implementing boolean logic based on computing-in-memory transistor
US-2023223939-A1 · Jul 13, 2023 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Zhejiang Lab | 5 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H03K19/21 | 2 |
| G11C11/223 | 2 |
| H03K19/20 | 2 |
| H03K19/1776 | 2 |
| H03K19/08 | 2 |