Full adder circuit and multi-bit full adder

Patent metadata

Field	Value
Publication number	US-12073192-B2
Application number	US-202318488991-A
Country	US
Kind code	B2
Filing date	Oct 17, 2023
Priority date	Aug 31, 2022
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

The present application discloses a full adder circuit and a multi-bit full adder. In the full adder circuit, an in-memory computing field-effect transistor stores data and performs logic operation on the data in the transistor and the loaded data according to different input signals; and a low-area full adder circuit is realized with very few transistors through the characteristics and the reading and writing modes of the in-memory computing field-effect transistor. The full adder circuit has a simple structure, which is greatly reduces the area and complexity of the full adder circuit, and saves 19 transistors compared with the traditional CMOS full adder circuits.

First claim

What is claimed is:

1. A low-area full adder circuit based on nonvolatile in-memory computing field-effect transistors, comprising:
a sum generating circuit comprising six in-memory computing field-effect transistors, wherein the sum generating circuit is configured to receive a first input signal, a second input signal and a third input signal, and output a first output signal; and
a carry generating circuit coupled to the sum generating circuit and comprising three in-memory computing field-effect transistors, wherein the carry generating circuit is configured to receive the first input signal and the second input signal from the sum generating circuit, receive the third input signal, and output a second output signal;
wherein the first output signal is a result of a summation logic operation of the first input signal, the second input signal and the third input signal, and the second output signal is a result of a carry logic operation of the first input signal, the second input signal and the third input signal;
and wherein the sum generating circuit comprises:
a first in-memory computing field-effect transistor, a threshold voltage of the first in-memory computing field-effect transistor is configured to receive the first input signal, and a gate voltage of the first in-memory computing field-effect transistor is configured to receive the second input signal;
a first parallel structure comprising a second in-memory computing field-effect transistor and a third in-memory computing field-effect transistor, wherein a threshold voltage of the second in-memory computing field-effect transistor is a constant value, and a gate input signal of the second in-memory computing field-effect transistor is a drain output signal of the first in-memory computing field-effect transistor; wherein a threshold voltage of the third in-memory computing field-effect transistor is configured to receive the first input signal, and a gate voltage of the third in-memory computing field-effect transistor is configured to receive the second input signal;
a seventh in-memory computing field-effect transistor, a threshold voltage of the seventh in-memory computing field-effect transistor is configured to receive the third input signal, and a gate input signal of the seventh in-memory computing field-effect transistor is a drain output signal of the first parallel structure; and
a second parallel structure comprising an eighth in-memory computing field-effect transistor and a ninth in-memory computing field-effect transistor, wherein a threshold voltage of the eighth in-memory computing field-effect transistor is a constant value, and a gate input signal of the eighth in-memory computing field-effect transistor is a drain output signal of the seventh in-memory computing field-effect transistor; wherein a threshold voltage of the ninth in-memory computing field-effect transistor is configured to receive the third input signal, a gate input signal of the ninth in-memory computing field-effect transistor is the same as the gate input signal of the seventh in-memory computing field-effect transistor, and a drain output signal of the second parallel structure is the first output signal.

2. The low-area full adder circuit based nonvolatile in-memory computing field-effect transistors according to claim 1 , wherein the sum generating circuit comprises:
the first in-memory computing field-effect transistor, a source terminal of the first in-memory computing field-effect transistor is grounded, and a drain terminal of the first in-memory computing field-effect transistor is connected to a pull-up resistor;
the first parallel structure comprising the second in-memory computing field-effect transistor and the third in-memory computing field-effect transistor, wherein a drain terminal of the first parallel structure is connected to the pull-up resistor, a source terminal of the first parallel structure is connected to a small resistor, and the other end of the small resistor is grounded; a gate terminal of the second in-memory computing field-effect transistor is connected to the drain terminal of the first in-memory computing field-effect transistor;
the seventh in-memory computing field-effect transistor, a source terminal of the seventh in-memory computing field-effect transistor is grounded, a drain terminal of the seventh in-memory computing field-effect transistor is connected to the pull-up resistor, and a gate terminal of the seventh in-memory computing field-effect transistor is connected to the drain terminal of the first parallel structure; and
the second parallel structure comprising the eighth in-memory computing field-effect transistor and the ninth in-memory computing field-effect transistor, wherein a drain terminal of the second parallel structure is connected to the pull-up resistor, and a source terminal of the second parallel structure is grounded; a gate terminal of the eighth in-memory computing field-effect transistor is connected to the drain terminal of the seventh in-memory computing field-effect transistor.

3. A low-area full adder circuit based on nonvolatile in-memory computing field-effect transistors, comprising:
a sum generating circuit comprising six in-memory computing field-effect transistors, wherein the sum generating circuit is configured to receive a first input signal, a second input signal and a third input signal, and output a first output signal; and
a carry generating circuit coupled to the sum generating circuit and comprising three in-memory computing field-effect transistors, wherein the carry generating circuit is configured to receive the first input signal and the second input signal from the sum generating circuit, receive the third input signal, and output a second output signal;
wherein the first output signal is a result of a summation logic operation of the first input signal, the second input signal and the third input signal, and the second output signal is a result of a carry logic operation of the first input signal, the second input signal and the third input signal;
wherein the carry generating circuit comprises:
a third parallel structure comprising a fourth in-memory computing field-effect transistor, a fifth in-memory computing field-effect transistor and a sixth in-memory computing field-effect transistor,
wherein a threshold voltage of the fourth in-memory computing field-effect transistor is configured to receive the third input signal, and a gate input signal of the fourth in-memory computing field-effect transistor is a constant value;
wherein a threshold voltage of the fifth in-memory computing field-effect transistor is configured to receive the first input signal, and a gate voltage of the fifth in-memory computing field-effect transistor is configured to receive the second input signal;
wherein a threshold voltage of the sixth in-memory computing field-effect transistor is configured to receive the first input signal, and a gate voltage of the sixth in-memory computing field-effect transistor is configured to receive the second input signal; and
wherein a source output signal of the third parallel structure is the second output signal.

4. The low-area full adder circuit based on nonvolatile in-memory computing field-effect transistors according to claim 3 , wherein the carry generating circuit comprises:
the third parallel structure comprising the fourth in-memory computing field-effect transistor, the fifth in-memory computing field-effect transistor and the sixth in-memory computing field-effect transistor,
wherein a source terminal of the fourth in-memory computing field-effect transistor is connected to a drain terminal of the fifth in-memory computing field-effect transistor to form a first series structure,
wherein a drain terminal of the fourth in-memory computing field-effect transis

Assignees

• Zhejiang Lab

Inventors

• Gu Jiani
• Yu Xiao

Classifications

• G06F7/501

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• G06F7/503 Primary

  using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal · CPC title