Communication method for multi-chip neural network algorithm based on FPGA main control

Patent metadata

Field	Value
Publication number	US-12019571-B1
Application number	US-202318389783-A
Country	US
Kind code	B1
Filing date	Dec 20, 2023
Priority date	Mar 17, 2023
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A communication method for a multi-chip neural network algorithm based on a FPGA main control, which designs original data frames, status frames, layered data frames, layered weight frames, computation result frames, layered data request frames, layered weight request frames, computation result request frames and running status request frames, and then completes image processing based on the neural network algorithm according to the scheduling of transmitting and receiving processes. The present disclosure ensure that communication of multi-layer data structures and various data types based on the neural network algorithm, and accurately schedules the transmitting and receiving of data required by the main control and each chip in the multi-chip system, and sends out data request commands; it plays a very active role in receiving, transmitting and feeding back the running status of the chip and the errors and error types.

First claim

What is claimed is:

1. A communication method for a multi-chip neural network algorithm based on a Field Programmable Gate Array (FPGA) main control, comprising:
step (1), constructing a frame structure by a multi-chip structure based on the FPGA main control, wherein the frame structure comprises an original data frame, a status frame, a layered data frame, a layered weight frame, a computation result frame, a layered data request frame, a layered weight request frame, a computation result request frame and an running status request frame; and guiding a FPGA main control interface module and a chip data reception module by the multi-chip structure based on the FPGA main control to realize data communication for a chip or a chipset;
step (2), initiating the data transmission by the original data frame or the request frame, comprising data transmission and data request from the FPGA main control to the chip or the chipset, and data request from the chip or the chipset to the FPGA main control;
step (3), transmitting data from the FPGA main control to the chip or the chipset, storing and computing data after receiving the data by the chip, and transmitting a computation result to the FPGA main control; wherein when a transmission error occurs in a de-framing and verification process during transmission of the FPGA main control, an error frame is transmitted by a receiver; and when there are status requests and control requirements during the transmission of the FPGA main control, the status requests or control commands are transmitted by the FPGA main control to the chip or the chipset; and
step (4), transmitting a data transmission request frame from the FPGA main control to the chip or the chipset, and transmitting the data or data storage or computation result to the FPGA main control after receiving the data transmission request frame by the chip; requesting data from the FPGA main control to the chip, and transmitting the data from the FPGA main control to the chip or the chipset; wherein when a transmission error occurs in the de-framing and verification process during transmission of the FPGA main control, the receiver transmitting an error frame; when there are status requests and control requirements during the transmission of the FPGA main control, the FPGA main control transmitting the status requests or control commands to the chip or the chipset.

2. The communication method for a multi-chip neural network algorithm based on a FPGA main control according to claim 1 , wherein the frame structure comprises:
the original data frame comprising a frame instruction segment, a numerical status segment, a data segment and a verification segment; wherein the frame instruction segment comprises a frame start code, a frame identification code and a frame type code; the numerical status segment is a data structure, comprising a frame start code, an image frame height and an image frame width; the data segment comprises data to be transmitted grouped into sets of 32 bits for each transmission according to the data to be transmitted, a data arrangement mode is from a bottom bit to a high bit, and the high bit is supplemented by 0 for a last data segment less than 32 bits; and the verification segment adopts a checksum method to negate all data values of the frame instruction segment, the numerical status segment, the data segment and the verification segment by 1, and the data values are arranged from high to low, with high bits less than 32 bits being supplemented by 0, and the high bits exceeding 32 bits being reduced by 32 bits;
the status frame comprising a frame instruction segment and a numerical status segment; wherein the frame instruction segment comprises a frame start code, a frame identification code and a frame type code, and the numerical status segment comprises a receiving correct status, a data counting error status, a data verification error status and a chip running error status;
the layered data frame, the layered weight frame and the computation result frame all comprising a frame instruction segment, a numerical status segment, a data segment and a verification segment; wherein the frame instruction segment comprises a frame start code, a frame identification code and a frame type code; the numerical status segment comprises a data length code, layer number information, an image frame height and an image frame width; a framing method of the data segment is consistent with the original data frame; and a verification method of the verification segment is consistent with the original data frame;
the layered data request frame, the layered weight request frame and the computation result request frame all comprising a frame instruction segment and a numerical status segment, and the layered data request frame, the layered weight request frame and the computation result request frame being used for requesting the layered data frame, the layered weight frame and the computation result frame, respectively; wherein the frame instruction segment comprises a frame start code, a frame identification code and a frame type code; and the numerical status segment comprises a data length code, layer number information, an image frame height and an image frame width; and
the running status request frame comprising a frame instruction segment and a numerical status segment; wherein the frame instruction segment comprises a frame start code, a frame identification code and a frame type code; and the numerical status segment comprises a frame reception completion status, a frame reception error status, a chip status request frame, a main control FPGA status request frame and a status command given to the chip by the FPGA main control.

3. The communication method for a multi-chip neural network algorithm based on a FPGA main control according to claim 1 , wherein the multi-chip structure based on the FPGA main control comprises one FPGA main control system and a plurality of chip nodes; and the FPGA main control system is connected with each chip node through a data connection line and a chip selection signal line.

4. A communication device for a multi-chip neural network algorithm based on a FPGA main control, comprising one or more processors configured for implementing the communication method for a multi-chip neural network algorithm based on a FPGA main control according to claim 1 .

5. A computer-readable storage medium on which a program is stored, wherein the program, when executed by a processor, is configured to implement the communication method for a multi-chip neural network algorithm based on a FPGA main control according to claim 1 .

6. The communication method for a multi-chip neural network algorithm based on a FPGA main control according to claim 2 , further comprising:
controlling the transmission of the chip or the chipset by adjusting a structure of the frame instruction segment; transmitting the data at a first 32 bits of each frame to guide the FPGA main control interface module and the chip data reception module, and transmitted corresponding frame information to the chip or the chipset corresponding to the frame identification code according to the frame type code; wherein the frame instruction segment comprises transmitting according to a data number, repeated transmitting with a first bit being ignored, repeated transmitting with a first bit and a second bit being ignored, repeated transmitting with a first bit, a second bit and a third bit being ignored, repeated transmitting with a first bit, a second bit, a third bit and a fourth bit being ignored, repeated transmitting of all bits, allowing the data to be transmitted to the corresponding chip or the corresponding 2, 4, 8, 16 and 32 chips to repeatedly send the data.

7. The communication method for a multi-chip ne

Assignees

• Zhejiang Lab

Inventors

• Yan Li
• Ren Songnan
• Liu Zhiwei
• Hu Tang
• Li Xiangdi
• Gu Jiani
• Hao Chunling
• Yu Xiao

Classifications

• G06F13/20 Primary

  for access to input/output bus · CPC title

• G06F2213/40

  Bus coupling · CPC title