Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures

Patent metadata

Field	Value
Publication number	US-11095313-B2
Application number	US-201916659241-A
Country	US
Kind code	B2
Filing date	Oct 21, 2019
Priority date	Oct 21, 2019
Publication date	Aug 17, 2021
Grant date	Aug 17, 2021

Abstract

Single error correction (“SEC”) code and triple error detection (“TED”) code are used to optimize bandwidth and resilience under multiple bit failures. One or more errors in data stored in duplicated registers are detected and corrected using the SEC code and TED code where simultaneous read operations are produced with two copies of data for each of the duplicated registers for a multi-port banked memory array. The SEC code and TED code may be included in each of the two data copies of the simultaneous read operations.

First claim

The invention claimed is:

1. A method, by a processor, for providing enhanced error correction using a single error correction (SEC) code and triple error detection (TED) code in a computing system, comprising:
receiving a request to read data respectively stored in duplicated registers of a multi-port banked memory array, wherein two copies of the data are maintained for each of the duplicated registers of the multi-port banked memory array,
responsive to receiving the request to read the data stored in the duplicated registers, determining that one or more correctable errors exist in a first copy or a second copy of the two copies of the data; and
correcting the one or more correctable errors in at least one of the first copy and the second copy of the two copies of the data stored in the duplicated registers using an SEC code and TED code encoded in each of the two copies of the data stored in the duplicated registers, wherein the SEC code and TED code are each utilized to correct up to three aggregate correctable errors irrespective of which of the first copy and the second copy stored in the duplicated registers the data having the up to three aggregate correctable errors exists.

2. The method of claim 1 , further including reading the data from a selected port in the multi-port banked memory array upon the SEC code and TED code failing to detect an error in the data.

3. The method of claim 1 , further including:
reading the data from the second copy of the data in a selected port in the multi-port banked memory array upon the SEC code and TED code detecting the one or more correctable errors exist within the first copy of the data; and
correcting the one or more correctable errors in the the first copy of the data.

4. The method of claim 1 , further including, responsive to detecting the one or more correctable errors exist in the first copy of the data, satisfying the request to read the data using the second copy of the data, wherein the second copy of the data is inclusive of corrected data generated from previously detected and corrected errors.

5. The method of claim 1 , further including indicating the one or more correctable errors in the first copy of the data and the second copy of the data are uncorrectable upon each of the two copies of the data producing different, corrected data.

6. A system for providing enhanced error correction using single error correction (SEC code) and triple error detection (TED code) in a computing system, comprising:
one or more computers with executable instructions that when executed cause the system to:
receive a request to read data respectively stored in duplicated registers of a multi-port banked memory array, wherein two copies of the data are maintained for each of the duplicated registers of the multi-port banked memory array;
responsive to receiving the request to read the data stored in the duplicated registers, determine that one or more correctable errors exist in a first copy or a second copy of the two copies of the data; and

correct the one or more correctable errors in at least one of the first copy and the second copy of the two copies of the data stored in the duplicated registers using an SEC code and TED code encoded in each of the two copies of the data stored in the duplicated registers, wherein the SEC code and TED code are each utilized to correct up to three aggregate correctable errors irrespective of which of the first copy and the second copy stored in the duplicated registers the data having the up to three aggregate correctable errors exists.

7. The system of claim 6 , wherein the executable instructions read the data from a selected port in the multi-port banked memory array upon the SEC code and TED code failing to detect an error in the data.

8. The system of claim 6 , wherein the executable instructions:
read the data from the second copy of the data in a selected port in the multi-port banked memory array upon the SEC code and TED code detecting the one or more correctable errors exist within the first copy of the data; and
correct the one or more correctable errors in the the first copy of the data.

9. The system of claim 6 , wherein the executable instructions, responsive to detecting the one or more correctable errors exist in the first copy of the data, satisfy the request to read the data use the second copy of the data, wherein the second copy of the data is inclusive of corrected data generated from previously detected and corrected errors.

10. The system of claim 6 , wherein the executable instructions indicate the one or more correctable errors in the first copy of the data and the second copy of the data are uncorrectable upon each of the two copies of the data producing different, corrected data.

11. A computer program product for providing enhanced error correction using single error correction (SEC code) and triple error detection (TED code) in a computing system by a processor, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising:
an executable portion that receives a request to read data respectively stored in duplicated registers of a multi-port banked memory array, wherein two copies of the data are maintained for each of the duplicated registers of the multi-port banked memory array;
an executable portion that, responsive to receiving the request to read the data stored in the duplicated registers, determines that one or more correctable errors exist in a first copy or a second copy of the two copies of the data; and
an executable portion that corrects the one or more correctable errors in at least one of the first copy and the second copy of the two copies of the data stored in the duplicated registers using an SEC code and TED code encoded in each of the two copies of the data stored in the duplicated registers, wherein the SEC code and TED code are each utilized to correct up to three aggregate correctable errors irrespective of which of the first copy and the second copy stored in the duplicated registers the data having the up to three aggregate correctable errors exists.

12. The computer program product of claim 11 , further including an executable portion that reads the data from a selected port in the multi-port banked memory array upon the SEC code and TED code failing to detect an error in the data.

13. The computer program product of claim 11 , further including an executable portion that:
reads the data from the second copy of the data in a selected port in the multi-port banked memory array upon the SEC code and TED code detecting the one or more correctable errors exist within the first copy of the data; and
corrects the one or more correctable errors in the the first copy of the data.

14. The computer program product of claim 11 , further including an executable portion that,
responsive to detecting the one or more correctable errors exist in the first copy of the data, satisfies the request to read the data uses the second copy of the data, wherein the second copy of the data is inclusive of corrected data generated from previously detected and corrected errors.

15. The computer program product of claim 11 , further including an executable portion that indicates the one or more correctable errors in the first copy of the data and the second copy of the data are uncorrectable upon each of the two copies of the data producing different, corrected data.

Assignees

• IBM

Inventors

• Montoye Robert
• Derby Jeffrey
• Fleischer Bruce
• Nair Prashant Jayaprakash

Classifications

• H03M13/2906 Primary

  using block codes (H03M13/2957 takes precedence) · CPC title

• H03M13/19 Primary

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• G06F11/1666

  where the redundant component is memory or memory area · CPC title

• H03M13/095

  Error detection codes other than CRC and single parity bit codes · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title