Resolving operand store compare conflicts

US10824430B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-10824430-B1
Application numberUS-201916394056-A
CountryUS
Kind codeB1
Filing dateApr 25, 2019
Priority dateApr 25, 2019
Publication dateNov 3, 2020
Grant dateNov 3, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Managing program instruction execution by receiving a first OSC (operand store compare) instruction, the first OSC instruction comprising a first itag and a first instruction address and creating a first OSC table entry according to the first itag and first instruction address. Further, receiving a second OSC instruction, the second OSC instruction comprising a second itag and a second instruction address and creating a second OSC table entry according to the second itag and an itag delta between the first itag and the second itag, then appending the second OSC table entry according to an itag delta between the second itag and a third itag, and providing an itag delta from the second OSC table entry to an instruction sequencing unit (ISU).

First claim

Opening claim text (preview).

What is claimed is: 1. A computer implemented method for managing application execution, the method comprising: receiving a first OSC (operand store compare) instruction, the first OSC instruction comprising a first instruction tag (itag) and a first instruction address; creating a first OSC table entry according to the first itag and first instruction address; receiving a second OSC instruction, the second OSC instruction comprising a second itag and a second instruction address; creating a second OSC table entry according to the second itag and an itag delta between the first itag and the second itag; appending the second OSC table entry according to an itag delta between the second itag and a third itag; and providing an itag delta from the second OSC table entry to an ISU (instruction sequencing unit). 2. The computer implemented method according to claim 1 , further comprising creating a dependency between the first OSC instruction and the second OSC instruction according to an itag delta. 3. The computer implemented method according to claim 1 , wherein providing an itag delta from the second OSC table entry to an ISU comprises providing a youngest itag delta from the second OSC table entry to the ISU. 4. The computer implemented method according to claim 1 , further comprising: appending a hash value of a GHV (global history vector) associated with an itag delta value to the second OSC table entry; and providing an itag delta to the ISU according to the hash value of the GHV. 5. The computer implemented method according to claim 4 , further comprising: determining a hash value of a GHV associated with the first OSC table entry; matching the hash value of the GHV associated with the first OSC table entry and the hash value of the GHV associated with an itag delta value of the second OSC table entry; and providing the itag delta value of the second OSC table entry associated with the hash value of the GHV of the second OSC table entry to the ISU. 6. The computer implemented method according to claim 1 , further comprising: appending an LHV (local history vector) to the second OSC table entry, wherein the LHV comprises a set of itag delta values; and providing an itag delta to the ISU according to the LHV. 7. The computer implemented method according to claim 1 , wherein the first OSC instruction comprises a store instruction and the second OSC instruction comprises a load instruction. 8. A computer program product for managing application execution, the computer program product comprising one or more computer readable storage devices and stored program instructions on the one or more computer readable storage devices, the stored program instructions comprising: programmed instructions for receiving a first OSC (operand store compare) instruction, the first OSC instruction comprising a first itag and a first instruction address; programmed instructions for creating a first OSC table entry according to the first itag and first instruction address; programmed instructions for receiving a second OSC instruction, the second OSC instruction comprising a second itag and a second instruction address; programmed instructions for creating a second OSC table entry according to the second itag and an itag delta between the first itag and the second itag; programmed instructions for appending the second OSC table entry according to an itag delta between the second itag and a third itag; and programmed instructions for providing an itag delta from the second OSC table entry to an ISU (instruction sequencing unit). 9. The computer program product according to claim 8 , the stored program instructions further comprising: programmed instructions for creating a dependency between the first OSC instruction and the second OSC instruction according to an itag delta. 10. The computer program product according to claim 8 , wherein providing an itag delta from the second OSC table entry to an ISU comprises providing a youngest itag delta from the second OSC table entry to the ISU. 11. The computer program product according to claim 8 , the stored program instructions further comprising: programmed instructions for appending a hash value of a GHV (global history vector) associated with an itag delta value to the second OSC table entry; and programmed instructions for providing an itag delta to the ISU according to the hash value of the GHV. 12. The computer program product according to claim 11 , the stored program instructions further comprising: programmed instructions for determining a hash value of a GHV associated with the first OSC table entry; programmed instructions for matching the hash value of the GHV associated with the first OSC table entry and the hash value of the GHV associated with an itag delta value of the second OSC table entry; and programmed instructions for providing the itag delta value of the second OSC table entry associated with the hash value of the GHV of the second OSC table entry to the ISU. 13. The computer program product according to claim 8 , the stored program instructions further comprising: programmed instructions for appending an LHV (local history vector) to the second OSC table entry, wherein the LHV comprises a set of itag delta values; and programmed instructions for providing an itag delta to the ISU according to the LHV. 14. The computer program product according to claim 8 , wherein the first OSC instruction comprises a store instruction and the second OSC instruction comprises a load instruction. 15. A computer system for managing application execution, the computer system comprising: one or more computer processors; one or more computer readable storage devices; stored program instructions on the one or more computer readable storage devices for execution by the at least one or more computer processors, the stored program instructions comprising: programmed instructions for receiving a first OSC (operand store compare) instruction, the first OSC instruction comprising a first itag and a first instruction address; programmed instructions for creating a first OSC table entry according to the first itag and first instruction address; programmed instructions for receiving a second OSC instruction, the second OSC instruction comprising a second itag and a second instruction address; programmed instructions for creating a second OSC table entry according to the second itag and an itag delta between the first itag and the second itag; programmed instructions for appending the second OSC table entry according to an itag delta between the second itag and a third itag; and programmed instructions for providing an itag delta from the second OSC table entry to an ISU (instruction sequencing unit). 16. The computer system according to claim 15 , the stored program instructions further comprising: programmed instructions for creating a dependency between the first OSC instruction and the second OSC instruction according to an itag delta. 17. The computer system according to claim 15 , wherein providing an itag delta from the second OSC table entry to an ISU comprises providing a youngest itag delta from the second OSC table entry to the ISU. 18. The computer system according to claim 15 , the stored program instructions further comprising: programmed instructions for appending a hash value of a GHV (global history vector) associated with an itag delta value to the second OSC table entry; and programmed instructions for providing an itag delta to the ISU according to the hash val

Assignees

Inventors

Classifications

  • Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

  • G06F9/3838Primary

    Dependency mechanisms, e.g. register scoreboarding · CPC title

  • G06F9/3834Primary

    Maintaining memory consistency · CPC title

  • to perform miscellaneous control operations, e.g. NOP · CPC title

  • LOAD or STORE instructions; Clear instruction · CPC title

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What does patent US10824430B1 cover?
Managing program instruction execution by receiving a first OSC (operand store compare) instruction, the first OSC instruction comprising a first itag and a first instruction address and creating a first OSC table entry according to the first itag and first instruction address. Further, receiving a second OSC instruction, the second OSC instruction comprising a second itag and a second instruct…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F9/3838. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 03 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).