Significand shifting in floating point processing operations

Patent metadata

Field	Value
Publication number	US-12423097-B2
Application number	US-202418428137-A
Country	US
Kind code	B2
Filing date	Jan 31, 2024
Priority date	Jan 31, 2024
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

Apparatuses, methods, computer readable media, and systems are disclosed in which a floating point processing instruction is decoded to generate control signals to trigger a floating point processing operation. In response to the control signals, the floating point processing operation is performed, comprising: performing processing that yields more than two floating point values; and performing, for each of the more than two floating point values: a determination of a shift value for a significand of that floating point value by subtracting an exponent value for that floating point value from a predetermined constant anchor value determined based on a maximum calculable product exponent for a product of the more than two floating point operands, and a shift of the significand by the shift value determined for that floating point value.

First claim

We claim:

1. Apparatus comprising:
decoder circuitry responsive to a floating point processing instruction to generate control signals to trigger a floating point processing operation; and
processing circuitry responsive to the control signals to perform the floating point processing operation, the floating point processing operation comprising:
performing processing that yields more than two floating point values; and
performing, for each of the more than two floating point values:
a determination of a shift value for a significand of that floating point value by subtracting an exponent value for that floating point value from a predetermined constant anchor value, wherein the predetermined constant anchor value is determined based on a maximum calculable product exponent for a product of the more than two floating point operands; and
a shift of the significand by the shift value determined for that floating point value.

2. The apparatus as claimed in claim 1 , wherein the floating point processing instruction is a dot product instruction and the floating point processing operation is a dot product operation.

3. The apparatus as claimed in claim 1 , wherein the floating point processing operation comprises an accumulation and the floating point processing instruction identifies an accumulation source from which a prior accumulation value is to be retrieved and into which an accumulation result of the floating point processing operation is to be accumulated.

4. The apparatus as claimed in claim 3 , wherein the dot product operation is a two-input dot product operation and the floating point processing instruction identifies two pairs of input floating point operands and the accumulation source.

5. The apparatus as claimed in claim 3 , wherein the dot product operation is a four-input dot product operation and the floating point processing instruction identifies four pairs of input floating point operands and the accumulation source.

6. The apparatus as claimed in claim 1 , wherein the predetermined constant anchor value is determined by a summation of the maximum calculable product exponent with a characteristic multiplicity factor dependent on a multiplicity of the more than two floating point values.

7. The apparatus as claimed in claim 6 , wherein the characteristic multiplicity factor is determined as a ceiling value of a base-2 logarithm of the multiplicity of the more than two floating point values.

8. The apparatus as claimed in claim 6 , wherein the dot product operation is a two-input or a four-input dot product operation and the floating point processing instruction identifies two pairs or four pairs of input floating point operands and the accumulation source, wherein the multiplicity of the more than two floating point values is given by a multiplicity of addends in the two-input dot product operation or the four-input dot product operation.

9. The apparatus as claimed in claim 7 , wherein the summation further comprises an increment value.

10. The apparatus as claimed in claim 9 , wherein the increment value is 1.

11. The apparatus as claimed in claim 3 , wherein the floating point processing instruction further specifies a scaling factor and the determination of the shift value for the prior accumulation value further comprises subtracting the scaling factor from the predetermined constant anchor value.

12. The apparatus as claimed in claim 3 , wherein the floating point processing instruction further specifies a scaling factor and the determination of the shift value for the prior accumulation value further comprises adding the scaling factor to the predetermined constant anchor value.

13. The apparatus as claimed in claim 3 , wherein a direction of the shift of the significand for the prior accumulation value is determined by a sign of the shift value and wherein the shift of the significand for the more than two floating point values is a right shift.

14. The apparatus as claimed in claim 4 , wherein a first floating point format of the prior accumulation value differs from a second floating point format for the input floating point operands in that the first floating point format encompasses all precise encodings of the second floating point format,
and wherein the shift of the significand for the prior accumulation value is a right shift and the shift of the significand for others of the more than two floating point values is a right shift.

15. The apparatus as claimed in claim 14 , wherein the first floating point format comprises 16 bits and the second floating point format comprises 8 bits.

16. A non-transitory computer-readable medium on which is stored computer-readable code for fabrication of the apparatus of claim 1 .

17. A method of data processing comprising:
decoding a floating point processing instruction specifying a floating point processing operation;
generating control signals to trigger the floating point processing operation; and
performing the floating point processing operation in response to the control signals, the floating point processing operation comprising:
performing processing that yields more than two floating point values; and
performing, for each of the more than two floating point values:

a determination of a shift value for a significand of that floating point value by subtracting an exponent value for that floating point value from a predetermined constant anchor value, wherein the predetermined constant anchor value is determined based on a maximum calculable product exponent for a product of the more than two floating point operands; and
a shift of the significand by the shift value determined for that floating point value.

18. A system comprising:
the apparatus of claim 1 , implemented in at least one packaged chip;
at least one system component; and
a board,
wherein the at least one packaged chip and the at least one system component are assembled on the board.

19. A chip-containing product comprising the system of claim 18 assembled on a further board with at least one other product component.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Saini Anisha
• Kroes Mairin Imro
• Elmer Thomas
• Burgess Neil

Classifications

• G06F9/30032 Primary

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F7/49942 Primary

  Significance control · CPC title