Correlating pseudonoise sequences in an simd processor

Patent metadata

Field	Value
Publication number	US-2016020821-A1
Application number	US-201414336430-A
Country	US
Kind code	A1
Filing date	Jul 21, 2014
Priority date	Jul 21, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

In one embodiment, a method includes receiving a signal having communication data from two or more mobile devices, each identifiable by an associated pseudonoise sequence. A first mobile device is identifiable by a first pseudonoise sequence. Two or more samples of the received signal are stored in an input register. A segment of the first pseudonoise sequence is stored as a bit vector in a second register. The SIMD instruction is processed, by an SIMD processor, to produce correlation values associated with the segment of the first pseudonoise sequence and the samples of the received signal. Processing the SIMD instruction includes distributing the segment of the first pseudonoise sequence, as a bit vector, across two or more lanes of the SIMD processor. The processing contributes to despreading the received signal, and an output of the processing includes at least a portion of the communication data from the first mobile device.

First claim

What is claimed is:

1 . A computer-implemented method, comprising:
receiving a signal comprising communication data from two or more mobile devices, wherein each of the two or more mobile devices is identifiable by an associated pseudonoise sequence, and wherein a first mobile device of the two or more mobile devices is identifiable by an associated first pseudonoise sequence; storing two or more samples of the received signal in an input register; storing a segment of the first pseudonoise sequence as a bit vector in a second register; and processing the SIMD instruction, by an SIMD processor, to produce correlation values associated with the segment of the first pseudonoise sequence in the second register and the two or more samples of the received signal in the input register; wherein the processing of the SIMD instruction comprises distributing the segment of the first pseudonoise sequence, as stored as the bit vector in the second register, across two or more lanes of the SIMD processor; and wherein the processing of the SIMD instruction contributes to despreading the received signal, and wherein an output of the processing of the SIMD instruction comprises at least a portion of the communication data from the first mobile device.

2 . The method of claim 1 , wherein each data element of the segment of the first pseudonoise sequence comprises no more than two bits in the bit vector representing the segment of the first pseudonoise sequence.

3 . The method of claim 1 , wherein the SIMD instruction indicates a location of the bit vector represented the segment of the first pseudonoise sequence within the second register.

4 . The method of claim 1 , wherein there exists a one-to-one association between bits in the bit vector representing the segment of the first pseudonoise sequence and data elements in the two or more samples of the received signal.

5 . The method of claim 1 , wherein there exists a one-to-one association between bits in the bit vector representing the segment of the first pseudonoise sequence and parallel computation paths in the SIMD processor.

6 . A system comprising:
a memory having computer readable instructions; and a processor configured to execute the computer readable instructions, the instructions comprising:
receiving a signal comprising communication data from two or more mobile devices, wherein each of the two or more mobile devices is identifiable by an associated pseudonoise sequence, and wherein a first mobile device of the two or more mobile devices is identifiable by an associated first pseudonoise sequence;
storing two or more samples of the received signal in an input register;
storing a segment of the first pseudonoise sequence as a bit vector in a second register; and
submitting the SIMD instruction to an SIMD processor for processing, to produce correlation values associated with the segment of the first pseudonoise sequence in the second register and the two or more samples of the received signal in the input register;
wherein the processing of the SIMD instruction comprises distributing the segment of the first pseudonoise sequence, as stored as the bit vector in the second register, across two or more lanes of the SIMD processor; and
wherein the processing of the SIMD instruction contributes to despreading the received signal, and wherein an output of the processing of the SIMD instruction comprises at least a portion of the communication data from the first mobile device.

7 . The system of claim 6 , wherein each data element of the segment of the first pseudonoise sequence comprises no more than two bits in the bit vector representing the segment of the first pseudonoise sequence.

8 . The system of claim 6 , wherein the SIMD instruction indicates a location of the bit vector represented the segment of the first pseudonoise sequence within the second register.

9 . The system of claim 6 , wherein there exists a one-to-one association between bits in the bit vector representing the segment of the first pseudonoise sequence and data elements in the two or more samples of the received signal.

10 . The system of claim 6 , wherein there exists a one-to-one association between bits in the bit vector representing the segment of the first pseudonoise sequence and parallel computation paths in the SIMD processor.

11 . A computer program product for despreading a received signal, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
receiving a signal comprising communication data from two or more mobile devices, wherein each of the two or more mobile devices is identifiable by an associated pseudonoise sequence, and wherein a first mobile device of the two or more mobile devices is identifiable by an associated first pseudonoise sequence; storing two or more samples of the received signal in an input register; storing a segment of the first pseudonoise sequence as a bit vector in a second register; and submitting the SIMD instruction to an SIMD processor for processing, to produce correlation values associated with the segment of the first pseudonoise sequence in the second register and the two or more samples of the received signal in the input register; wherein the processing of the SIMD instruction comprises distributing the segment of the first pseudonoise sequence, as stored as the bit vector in the second register, across two or more lanes of the SIMD processor; and wherein the processing of the SIMD instruction contributes to despreading the received signal, and wherein an output of the processing of the SIMD instruction comprises at least a portion of the communication data from the first mobile device.

12 . The computer program product of claim 11 , wherein each data element of the segment of the first pseudonoise sequence comprises no more than two bits in the bit vector representing the segment of the first pseudonoise sequence.

13 . The computer program product of claim 11 , wherein the SIMD instruction indicates a location of the bit vector represented the segment of the first pseudonoise sequence within the second register.

14 . The computer program product of claim 11 , wherein there exists a one-to-one association between bits in the bit vector representing the segment of the first pseudonoise sequence and data elements in the two or more samples of the received signal.

15 . The computer program product of claim 11 , wherein there exists a one-to-one association between bits in the bit vector representing the segment of the first pseudonoise sequence and parallel computation paths in the SIMD processor.

Assignees

• IBM

Inventors

• Derby Jeffrey H
• Sreedhar Dheeraj

Classifications

• H04B1/709 Primary

  Correlator structure · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title