Packet format adjustment technologies
US-12568157-B2 · Mar 3, 2026 · US
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Debbage Mark patents
Debbage Mark is listed as an inventor on 37 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Debbage Mark |
| Total patents | 37 |
| First publication | Dec 31, 2015 |
| Latest publication | Mar 3, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
System for storage of received messages
US-12438821-B2 · Oct 7, 2025 · US
Reliable transport architecture
US-2025300940-A1 · Sep 25, 2025 · US
Reliable transport architecture
US-12212502-B2 · Jan 28, 2025 · US
Direct memory writes by network interface of a graphics processing unit
US-12190405-B2 · Jan 7, 2025 · US
System, apparatus, and method for streaming input/output data
US-12177277-B2 · Dec 24, 2024 · US
Scalable protocol-agnostic reliable transport
US-12137001-B2 · Nov 5, 2024 · US
Packet header optimization in ethernet internet protocol networks
US-2023412712-A1 · Dec 21, 2023 · US
Direct memory writes by network interface of a graphics processing unit
US-2022351326-A1 · Nov 3, 2022 · US
Technologies for managing a latency-efficient pipeline through a network interface controller
US-11467885-B2 · Oct 11, 2022 · US
Recent patents
Latest publications not already listed above.
Communications for workloads
US-2022138021-A1 · May 5, 2022 · US
Switch-originated congestion messages
US-2022124035-A1 · Apr 21, 2022 · US
System for storage of received messages
US-2022124046-A1 · Apr 21, 2022 · US
Packet format adjustment technologies
US-2022116325-A1 · Apr 14, 2022 · US
Scalable protocol-agnostic reliable transport
US-2022085916-A1 · Mar 17, 2022 · US
System, apparatus, and method for streaming input/output data
US-2021281618-A1 · Sep 9, 2021 · US
Reliable transport architecture
US-2021119930-A1 · Apr 22, 2021 · US
Technologies for managing a latency-efficient pipeline through a network interface controller
US-2019068509-A1 · Feb 28, 2019 · US
Sending packets using optimized PIO write sequences without SFENCES
US-10073796-B2 · Sep 11, 2018 · US
Reliable out-of order end-to-end protocol with robust window state overflow management and a multi-node system using same
US-10044626-B2 · Aug 7, 2018 · US
System, method and apparatus for improving the performance of collective operations in high performance computing
US-10015056-B2 · Jul 3, 2018 · US
Optimized credit return mechanism for packet sends
US-9984020-B2 · May 29, 2018 · US
Optimized credit return mechanism for packet sends
US-2018039593-A1 · Feb 8, 2018 · US
Optimized credit return mechanism for packet sends
US-9792235-B2 · Oct 17, 2017 · US
Sending packets using optimized PIO write sequences without sfences and out of order credit returns
US-9785359-B2 · Oct 10, 2017 · US
Optimized credit return mechanism for packet sends
US-2017235693-A1 · Aug 17, 2017 · US
Sending packets using optimized PIO write sequences without sfences
US-9734077-B2 · Aug 15, 2017 · US
Sending packets using optimized pio write sequences without sfences
US-2017177516-A1 · Jun 22, 2017 · US
Sending packets using optimized PIO write sequences without sfences
US-9588899-B2 · Mar 7, 2017 · US
Sending packets using optimized pio write sequences without sfences
US-2017017465-A1 · Jan 19, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 32 |
| Lntel Corp | 5 |
| Heinz Michael | 1 |
| Rimmer Todd | 1 |
| Kunz James | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F13/4282 | 17 |
| G06F13/28 | 16 |
| G06F2213/0026 | 15 |
| G06F13/1673 | 14 |
| G06F5/065 | 14 |