Reliable transport architecture

US12212502B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12212502-B2
Application numberUS-202017084526-A
CountryUS
Kind codeB2
Filing dateOct 29, 2020
Priority dateOct 31, 2019
Publication dateJan 28, 2025
Grant dateJan 28, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Examples described herein relate to technologies for reliable packet transmission. In some examples, a network interface includes circuitry to: receive a request to transmit a packet to a destination device, select a path for the packet, provide a path identifier identifying one of multiple paths from the network interface to a destination and Path Sequence Number (PSN) for the packet, wherein the PSN is to identify a packet transmission order over the selected path, include the PSN in the packet, and transmit the packet. In some examples, if the packet is a re-transmit of a previously transmitted packet, the circuitry is to: select a path for the re-transmit packet, and set a PSN of the re-transmit packet that is a current packet transmission number for the selected path for the re-transmit packet. In some examples, a network interface includes circuitry to process a received packet to at least determine a Path Sequence Number (PSN) for the received packet, wherein the PSN is to provide an order of packet transmissions for a path associated with the received packet, process a second received packet to at least determine its PSN, and based on the PSN of the second received packet not being a next sequential value after the PSN of the received packet, cause transmission of a re-transmit request to a sender of the packet and the second packet.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: an endpoint sender network interface comprising: a physical layer interface and circuitry coupled to the physical layer interface, the circuitry to: receive a request to transmit a packet to a destination device, select a path for the packet, provide a path identifier identifying one of multiple paths from the network interface to a destination and Path Sequence Number (PSN) for the packet in the selected path, wherein the PSN is to identify a packet transmission order over the selected path, include the PSN in a reliability layer (RL) header of the packet, determine a second sequence number of the packet, wherein the second sequence number is to identify a packet transmission order of the packet relative to previously transmitted packets over the multiple paths, include the second sequence number in the RL header of the packet, store data for the packet comprising: the second sequence number, the path identifier, and the PSN, and transmit the packet, wherein the packet is to include an Ethernet header, Internet Protocol (IP) header, transport layer header, and reliable transport packet, the reliable transport packet comprises the RL header and RL data integrity value, the RL header is separate from the transport layer header, the RL data integrity value comprises a cyclic redundancy check (CRC) value, and if the packet is a re-transmit of a previously transmitted packet, the circuitry is to:  select a path for the re-transmit packet, and  set a PSN of the re-transmit packet that is a current packet transmission number for the selected path for the re-transmit packet. 2. The apparatus of claim 1 , wherein the circuitry is to: select a path for the re-transmit packet based on a congestion level of one or more available paths and to load balance path utilization, wherein the selected path is a same path or different path than that used to send the previously transmitted packet. 3. The apparatus of claim 1 , wherein the circuitry is to: determine to re-transmit a packet based on receipt of a non-data packet or data packet from a receiver, wherein the non-data packet or data packet comprise an indication of highest PSN received before a detected gap in received PSN values. 4. The apparatus of claim 1 , wherein the circuitry is to: store data of a path identifier and PSN for the transmitted packet and update the data to indicate packets for which acknowledgement was received from a receiver. 5. The apparatus of claim 1 , wherein the circuitry is to: request a switch to indicate congestion for one or more prioritized packet classes; process an indication of queue congestion for one or more prioritized packet classes; and modify one or more paths of packets in the one or more prioritized packet classes based on the indication of queue congestion for one or more prioritized packet classes. 6. The apparatus of claim 1 , wherein the circuitry is to: track and compare congestion on different paths to determine whether to move traffic from a congested path to an uncongested path. 7. The apparatus of claim 1 , comprising a server coupled to the circuitry, the server to provide data for transmission by the network interface controller. 8. The apparatus of claim 1 , wherein the transport layer header is consistent with User Datagram Protocol (UDP). 9. The apparatus of claim 1 , wherein the reliable transport packet includes an opcode that is to identify reliable transport packet content and protocol version number. 10. A network interface apparatus comprising: a physical layer interface and circuitry coupled to the physical layer interface, wherein the circuitry is to: process a received packet to at least determine a Path Sequence Number (PSN) and a second sequence number of the received packet, wherein the PSN is to provide an order of packet transmissions for a path associated with the received packet, the received packet is to include an Ethernet header, Internet Protocol (IP) header, transport layer header, and reliable transport packet, the reliable transport packet comprises a reliability layer (RL) header and RL data integrity value, the RL header is separate from the transport layer header, the RL header includes the PSN, the RL data integrity value comprises a cyclic redundancy check (CRC) value, the second sequence number is to identify a packet transmission order of the received packet relative to packets previously transmitted over multiple paths; process a second received packet to at least determine its PSN, based on the PSN of the second received packet not being a next sequential value after the PSN of the received packet, cause transmission of a re-transmit request to a sender of the packet and the second packet; and based on a third received packet being a re-transmit of a previously transmitted packet, the re-transmit packet includes a PSN that is a then-current packet transmission number for a selected path for the re-transmit packet. 11. The apparatus of claim 10 , wherein the circuitry is to: cause transmission of an acknowledgement of receipt for the received packet, with a highest PSN received and a range of PSN values to a sender of the received packet, wherein the range of PSN values comprises a starting PSN value and ending PSN value. 12. The apparatus of claim 10 , wherein the re-transmit request is provided in a data packet or a non-data packet. 13. The apparatus of claim 10 , comprising a server to process data from the received packet. 14. A method comprising: at a network interface: receiving a request to transmit a packet to a destination device; selecting a path, among multiple paths, for the packet; providing a Path Sequence Number (PSN) for the packet, wherein the PSN is to provide a packet transmission number for the packet using the selected path; including the PSN in the packet; including a second sequence number in the packet; based on the packet comprising a re-transmit of a previously transmitted packet: selecting a path for the re-transmit packet and setting a PSN of the re-transmit packet that is a current packet transmission number for the selected path for the re-transmit packet; and transmitting the packet, wherein: the packet includes an Ethernet header, Internet Protocol (IP) header, transport layer header, and reliable transport packet, the reliable transport packet comprises a reliability layer (RL) header and RL data integrity value, the RL header is separate from the transport layer header, the RL header includes the PSN, the second sequence number identifies a packet transmission order of a received packet relative to packets previously transmitted over the multiple paths, and the RL data integrity value comprises a cyclic redundancy check (CRC) value. 15. The method of claim 14 , comprising: at the network interface: determining to re-transmit a packet based on receipt of a non-data packet or data packet from a receiver, wherein the non-data packet or data packet comprise an indication of highest PSN received before a detected gap in PSN values and a range of PSN values, wherein the range of PSN values comprises a starting PSN value and ending PSN value. 16. The method of claim 14 , comprising: at the network interface: storing data of a path identifier and PSN for the transmitted packet and updating the data to indicate packets for which acknowledgement was received from a receiver. 17. A method comprising: at a network interface: processing a received packet to at least determine

Assignees

Inventors

Classifications

  • by balancing the load, e.g. traffic engineering · CPC title

  • Formats specially adapted for sequence numbers · CPC title

  • H04L47/34Primary

    ensuring sequence integrity, e.g. using sequence numbers · CPC title

  • Multipath · CPC title

  • H04L1/1621Primary

    Group acknowledgement, i.e. the acknowledgement message defining a range of identifiers, e.g. of sequence numbers · CPC title

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What does patent US12212502B2 cover?
Examples described herein relate to technologies for reliable packet transmission. In some examples, a network interface includes circuitry to: receive a request to transmit a packet to a destination device, select a path for the packet, provide a path identifier identifying one of multiple paths from the network interface to a destination and Path Sequence Number (PSN) for the packet, wherein …
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H04L47/34. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 28 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).