Low precision deep neural network enabled by compensation instructions

Patent metadata

Field	Value
Publication number	US-12056594-B2
Application number	US-201816020952-A
Country	US
Kind code	B2
Filing date	Jun 27, 2018
Priority date	Jun 27, 2018
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

A compensated deep neural network (compensated-DNN) is provided. A first vector having a set of components and a second vector having a set of corresponding components are received. A component of the first vector includes a first quantized value and a first compensation instruction, and a corresponding component of the second vector includes a second quantized value and a second compensation instruction. The first quantized value is multiplied with the second quantized value to compute a raw product value. The raw product value is compensated for a quantization error according to the first and second compensation instructions to produce a compensated product value. The compensated product value is added into an accumulated value for the dot product. The accumulated value is converted into an output vector of the dot product. The output vector includes an output quantized value and an output compensation instruction.

First claim

What is claimed is:

1. A computing device comprising:
a hardware processor; and
a storage device storing a set of instructions, wherein an execution of the set of instructions by the processor configures the computing device to perform, by one or more neurons of a compensated Deep Neural Network (DNN), acts comprising:
receiving a first vector having a set of components and a second vector having a set of corresponding components, wherein a component of the first vector comprises a first quantized value and a first compensation instruction, and a corresponding component of the second vector comprises a second quantized value and a second compensation instruction;
multiplying the first quantized value with the second quantized value to compute a raw product value;
determining, based on the first and second compensation instructions, not to compensate for quantization errors;
in response to determining not to compensate for quantization errors:
placing into a low power mode a compensation circuit configured to compensate the raw product value for a quantization error according to the first and second compensation instructions to produce a compensated product value and to add the compensated product value into an accumulated value for the dot product;
adding the raw product value into the accumulated value for the dot product without computing the compensated product value; and

converting the accumulated value into an output vector of the dot product, the output vector comprising an output quantized value and an output compensation instruction.

2. The computing device of claim 1 , wherein the output compensation instruction comprises a bit to indicate whether the output quantized value is to be compensated by an estimated quantization error.

3. The computing device of claim 1 , wherein:
the first compensation instruction comprises a first direction bit and a first magnitude bit for compensating a quantization error of the first quantized value; and
the second compensation instruction comprises a second direction bit and a second magnitude bit for compensating a quantization error of the second quantized value.

4. The computing device of claim 3 , wherein compensating the raw product value for a quantization error according to the first and second compensation instructions to produce a compensated product value, comprises:
shifting the first quantization value according to the first magnitude bit;
shifting the second quantization value according to the second magnitude bit;
adding the shifted first quantization value and the shifted second quantization value to produce a compensation value according to the first and second direction bits; and
adding the compensation value with the raw product value to produce the compensated product value.

5. The computing device of claim 1 , wherein execution of the set of instructions by the processor further configures the computing device to perform acts, comprising:
placing a compensation circuit in a low power mode upon determining that the first compensation instruction includes a bit that indicates that a quantization error of the first quantized value is less than a threshold and the second compensation instruction includes a bit that indicates that a quantization error of the second quantized value is less than a threshold.

6. The computing device of claim 1 , wherein the first compensation instruction comprises no more than four bits, comprising a direction bit, a zero compensation bit, and two or less magnitude bits.

7. An integrated circuit (IC) comprising:
a processing element circuit comprising one or more neurons of a compensated Deep Neural Network (DNN) configured to produce a dot product based on a first vector having a set of components and a second vector having a set of corresponding components, wherein a component of the first vector comprises a first quantized value and a first compensation instruction and a corresponding component of the second vector comprises a second quantized value and a second compensation instruction, the processing element circuit comprising:
a computation circuit configured to:
multiply the first quantized value with the second quantized value to compute a raw product value;
adding the raw product value into the accumulated value for the dot product without computing the compensated product value; and
determine, based on the first and second compensation instructions, not to compensate for quantization errors;

a compensation circuit configured to compensate the raw product value for a quantization error according to the first and second compensation instructions to produce a compensated product value; and
an accumulation circuit configured to add the compensated product value into an accumulated value for the dot product, wherein the computation circuit is further configured to in response to determining not to compensate for quantization errors, placing the compensation circuit into a low power mode.

8. The IC of claim 7 , wherein the processing element further comprises a conversion circuit configured to convert the accumulated value into an output vector of the dot-product, the output vector comprising an output quantized value and an output compensation instruction.

9. The IC of claim 8 , wherein the processing element is a first processing element, wherein the output vector is used as a vector to a second processing element that is configured to use the output quantized value to compute a second raw product value and compensate the second raw product according to the output compensation instruction.

10. The IC of claim 8 , wherein the output compensation instruction comprises a bit to indicate whether an estimated quantization error for the output quantized value is zero.

11. The IC of claim 7 , wherein:
the first compensation instruction comprises a first direction bit and a first magnitude bit for compensating a quantization error of the first quantized value; and
the second compensation instruction comprises a second direction bit and a second magnitude bit for compensating a quantization error of the second quantized value.

12. The IC of claim 11 , wherein compensating the raw product value for a quantization error according to the first and second compensation instructions to produce a compensated product value comprises:
shifting the first quantization value according to the first magnitude bit;
shifting the second quantization value according to the second magnitude bit;
adding the shifted first quantization value and the shifted second quantization value to produce a compensation value according to the first and second direction bits; and
adding the compensation value with the raw product value to produce the compensated product value.

13. The IC of claim 7 , wherein the compensation circuit is in a low power mode upon determining that the first compensation instruction includes a bit that indicates that an estimated quantization error of the first quantized value is zero and the second compensation instruction includes a bit that indicates that an estimated quantization error of the second quantized value is zero.

14. The IC of claim 7 , wherein the first compensation instruction comprises no more than four bits, comprising a direction bit, a zero compensation bit, and two or less magnitude bits.

15. A computer-implemented method for computing a dot-product by one or more neurons of a compensated Deep Neural Network (DNN), comprising:
receiving a first vector having a set of components and a second vector having a set of corresponding components, wherein a component of the first vector com

Assignees

• IBM

Inventors

• Venkataramani Swagath
• Jain Shubham
• Srinivasan Vijayalakshmi
• Choi Jungwook
• Chang Leland

Classifications

• G06N3/048

  Activation functions · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06N3/063 Primary

  using electronic means · CPC title