Memory circuit with negative voltage assist

Patent metadata

Field	Value
Publication number	US-9812191-B1
Application number	US-201615279944-A
Country	US
Kind code	B1
Filing date	Sep 29, 2016
Priority date	Sep 29, 2016
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A memory device includes: a memory array comprising a first plurality of bit cells arranged along a first column; and a negative bit line (NBL) circuit, coupled to the memory array. The NBL circuit includes: a first pair of conducting gates that are coupled to the first plurality of bit cells through a bit line (BL) and a bit bar line (BBL) of the first column, respectively; and a pair of trigger circuits, coupled to the first pair of conducting gates, respectively, and configured to monitor voltage levels present on the BL and BBL of the first column through the respective first pair of conducting gates, and based on the monitored voltage levels, to assert an NBL enable signal so as to cause a negative voltage to be applied on either the BL or the BBL of the first column.

First claim

What is claimed is:

1. A memory device, comprising:
a memory array comprising a first plurality of bit cells arranged along a first column; and
a negative bit line (NBL) circuit, coupled to the memory array, and comprising:
a first pair of conducting gates that are coupled to the first plurality of bit cells through a bit line (BL) and a bit bar line (BBL) of the first column, respectively; and
a pair of trigger circuits, coupled to the first pair of conducting gates, respectively, and configured to monitor voltage levels present on the BL and BBL of the first column through the respective first pair of conducting gates, and based on the monitored voltage levels, to assert an NBL enable signal so as to cause a negative voltage to be applied on either the BL or the BBL of the first column.

2. The memory device of claim 1 , further comprising an OR logic gate coupled to the pair of trigger circuits.

3. The memory device of claim 2 , wherein when the voltage level present on the BL is below a threshold, the OR logic gate asserts the NBL enable signal to a high logical state.

4. The memory device of claim 3 , wherein each of the first pair of conducting gates comprises a transmission (TX) gate and serves as a resistor that causes a voltage drop on the respective voltage level present on the BL and BBL.

5. The memory device of claim 4 , wherein the threshold is determined based on the voltage drop caused by the respective TX gate and a trip point of the respective trigger circuit that is about 30% of a supplied voltage of the memory device.

6. The memory device of claim 1 , further comprising:
an inverter, coupled to the pair of trigger circuits, and configured to receive the NBL enable signal; and
a boosting capacitor, coupled to the inverter, and configured to provide the negative voltage to either the BL or the BBL of the first column based on a logical state of the NBL enable signal.

7. The memory device of claim 1 , further comprising an input/output (I/O) circuit that is coupled to the memory array and includes the NBL circuit.

8. The memory device of claim 1 , wherein the memory array comprises a second plurality of bit cells arranged along a second column, and the NBL circuit comprises a second pair of conducting gates that are coupled to the second plurality of bit cells through a bit line (BL) and a bit bar line (BBL) of the second column, respectively.

9. The memory device of claim 8 , wherein the pair of trigger circuits, coupled to the second pair of conducting gates, respectively, and configured to monitor voltage levels present on the BL and BBL of the second column through the respective second pair of conducting gates, and based on the monitored voltage levels, to assert the NBL enable signal so as to cause the negative voltage to be applied on either the BL or the BBL of the second column.

10. The memory device of claim 1 , wherein the trigger circuit includes a Schmitt trigger.

11. A memory device, comprising:
a memory array comprising a first plurality of bit cells arranged along a first column; and
a negative bit line (NBL) circuit, coupled to the memory array, and comprising:
a first pair of PMOS transistors that are coupled to the first plurality of bit cells through a bit line (BL) and a bit bar line (BBL) of the first column, respectively; and
a pair of inverter circuits, coupled to the first pair of PMOS transistors, respectively, and configured to monitor voltage levels present on the BL and BBL of the first column through the respective first pair of PMOS transistors, and based on the monitored voltage levels, to assert an NBL enable signal so as to cause a negative voltage to be applied on either the BL or the BBL of the first column.

12. The memory device of claim 11 , further comprising an OR logic gate coupled to the pair of inverter circuits.

13. The memory device of claim 12 , wherein when the voltage level present on the BL is below a threshold, the OR logic gate asserts the NBL enable signal to a high logical state.

14. The memory device of claim 13 , wherein each of the first pair of PMOS transistors serves as a resistor that causes a voltage drop on the respective voltage level present on the BL and BBL.

15. The memory device of claim 14 , wherein the threshold is determined based on the voltage drop caused by the respective PMOS transistors and a trip point of the respective inverter circuit that is about 50% of a supplied voltage of the memory device.

16. The memory device of claim 11 , further comprising:
an inverter, coupled to the pair of inverter circuits, and configured to receive the NBL enable signal; and
a boosting capacitor, coupled to the inverter, and configured to provide the negative voltage to either the BL or the BBL of the first column based on a logical state of the NBL enable signal.

17. The memory device of claim 11 , wherein the memory array comprises a second plurality of bit cells arranged along a second column, and the NBL circuit comprises a second pair of PMOS transistors that are coupled to the second plurality of bit cells through a bit line (BL) and a bit bar line (BBL) of the second column, respectively.

18. The memory device of claim 17 , wherein the pair of inverter circuits, coupled to the second pair of PMOS transistors, respectively, and configured to monitor voltage levels present on the BL and BBL of the second column through the respective second pair of PMOS transistors, and based on the monitored voltage levels, to assert the NBL enable signal so as to cause the negative voltage to be applied on either the BL or the BBL of the second column.

19. A memory device, comprising
a memory array comprising a plurality of bit cells arranged along a column; and
a negative bit line (NBL) circuit, coupled to the memory array, and comprising:
a pair of transmission (TX) gates that are coupled to the plurality of bit cells through a bit line (BL) and a bit bar line (BBL) of the column, respectively;
a pair of trigger circuits, coupled to the pair of TX gates, respectively; and
an OR logic gate coupled to the pair of trigger circuits, wherein
the pair of trigger circuits configured to monitor voltage levels present on the BL and BBL of the column through the respective pair of TX gates, and based on the monitored voltage levels, to cause the OR logic gate to assert an NBL enable signal so as to cause a negative voltage to be applied on either the BL or the BBL of the column.

20. The memory device of claim 19 , wherein each of the pair of TX gates serves as a resistor that causes a voltage drop on the respective voltage level present on the BL and BBL.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chander Avinash
• Chen Yen-Huei

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title