Systems and methods for direct data access in multi-level cache memory hierarchies

Patent metadata

Field	Value
Publication number	US-10402344-B2
Application number	US-201414549065-A
Country	US
Kind code	B2
Filing date	Nov 20, 2014
Priority date	Nov 21, 2013
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Methods and systems for in direct data access in, e.g., multi-level cache memory systems are described. A cache memory system includes a cache location buffer configured to store cache location entries, wherein each cache location entry includes an address tag and a cache location table which are associated with a respective cacheline stored in a cache memory. The system also includes a first cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer, and a second cache memory configured to store cachelines, each cacheline having data and an identity of a corresponding cache location entry in the cache location buffer. Responsive to a memory access request for a cacheline, the cache location buffer generates access information using one of the cache location tables which enables access to the cacheline without performing a tag comparison at the one of the first and second cache memories.

First claim

What is claimed is:

1. A cache memory system comprising:
a cache location buffer configured to store cache location entries, wherein each cache location entry includes an address tag and at least one cache location table which are associated with a respective cacheline stored in a cache memory, wherein the cache location table indicates both a current level and a current way where the respective cacheline is currently stored;
a first cache memory configured to store cachelines, at least one cacheline having data and a location of a corresponding cache location entry in said cache location buffer, wherein the corresponding cache location entry is associated with at least one of the cacheline or the data;
a second cache memory configured to store cachelines, at least one cacheline having data and a location of a corresponding cache location entry in said cache location buffer, wherein the corresponding cache location entry is associated with at least one of the cacheline or the data; and
wherein, responsive to a memory access request for a requested cacheline, the cache location buffer generates access information using the at least one location table for one of said first and second cache memories which enables direct access to the requested cacheline without performing a tag comparison with the address tag associated with the requested cacheline since the at least one cache location table provides both the current level and the current way for the requested cacheline.

2. The cache memory system of claim 1 , further comprising:
an update mechanism configured to update said cache location table when an associated cacheline is moved to another location in the cache memory system.

3. The cache memory system of claim 1 , further comprising:
an associative structure configured to translate a physical address into an identity of the corresponding cache location entry for an associated cacheline corresponding to the physical address.

4. The cache memory system of claim 3 , wherein generating the access information includes using the associative structure to find the location of the requested cacheline in response to the memory access request from a coherence protocol.

5. The cache memory system of claim 3 , wherein generating the access information includes using the associative structure performs prior to adding a new cache location entry for a selected physical address to the cache location buffer in order to determine if an existing cache location entry in the cache location buffer is associated with the selected physical address.

6. The cache memory system of claim 3 , wherein generating the access information includes using the associative structure only for cachelines that are associated with an associated cache location entry in at least one cache location table in the cache location buffer.

7. The cache memory system of claim 1 , further comprising:
an indirection table including an indirection table entry that associates a selected cacheline and the corresponding cache location entry in the cache location buffer, wherein when a selected cache location entry is moved the indirection table entry in the indirection table is updated.

8. The cache memory system of claim 1 , wherein the first cache memory is a first level cache memory which is tracked by the cache location table and which is associated with a first cache memory bank and the second cache memory is another first level cache memory which is tracked by another cache location table and which is associated with a second cache memory bank, wherein the memory access request is an address, and wherein a portion of the address is used to select whether to access the first cache memory bank or the second cache memory bank.

9. The cache memory system of claim 8 , wherein two memory access requests are performed in parallel, one to the first cache memory bank and another to the second cache memory bank.

10. The cache memory system of claim 1 , wherein,
the cache location buffer is associated with only the first cache memory and wherein the cache location buffer is accessed using a virtual address to locate the requested cacheline stored in the first cache memory, and
the cache memory system includes another cache location buffer associated with the second cache memory which is accessed to locate the requested cacheline stored in the second cache memory.

11. The cache memory system of claim 10 , wherein the another cache location buffer uses a physical address to locate the requested cacheline stored in the second cache memory.

12. The cache memory system of claim 1 , wherein,
the memory access request includes a virtual address having a tag portion, an offset portion and an index portion,
the cache location buffer compares the tag portion with address tags in its cache location entries to identify the corresponding cache location entry that is associated with the requested cacheline
the cache memory system further comprises logic which uses the offset portion to identify a selected cache location table from multiple cache location entries whose address tag matches the tag portion; and
at least one of the first cache memory or the second cache memory uses the index portion and the selected cache location table to locate the requested cacheline.

13. The cache memory system of claim 1 , wherein the corresponding cache location entry is associated with the cacheline.

14. The cache memory system of claim 1 , wherein the corresponding cache location entry is associated with the data.

15. A cache memory access method comprising:
storing cache location entries in a cache location buffer, wherein each cache location entry includes an address tag and a cache location table which are associated with a respective cacheline stored in a cache memory, wherein the cache location table indicates both a current level and a current way where an associated cacheline is currently stored;
storing cachelines in a first cache memory, at least one cacheline having data and a location of a corresponding cache location entry in said cache location buffer, wherein the corresponding cache location entry is associated with at least one of the cacheline or the data; and
storing cachelines in a second cache memory, at least one cacheline having data and a location of a corresponding cache location entry in said cache location buffer, wherein the corresponding cache location entry is associated with at least one of the cacheline or the data; and
generating, responsive to a memory access request for a requested cacheline, access information for one of said first and second cache memories using the cache location table, which access information enables direct access to the requested cacheline without performing a tag comparison with an address tag associated with the requested cacheline since the cache location table provides both the current level and the current way for the requested cacheline.

16. The cache memory access method of claim 15 , further comprising:
updating said cache location table when the associated cacheline is moved to another location in the cache memory.

17. The cache memory access method of claim 16 , further comprising:
translating a selected physical address into an identity of the corresponding cache location entry that stores the cache location table for the requested cacheline corresponding to the selected physical address.

18. The cache memory access method of claim 17 , wherein the translating is performed in response to the memory access request received from a coherence protocol.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hagersten Erik
• Sembrant Andreas
• Black-Schaffer David
• Kaxiras Stefanos

Classifications

• G06F2212/655

  Same page detection · CPC title

• G06F12/1063

  the data cache being concurrently virtually addressed · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0864 Primary

  using pseudo-associative means, e.g. set-associative or hashing · CPC title

• G06F12/1054 Primary

  the data cache being concurrently physically addressed · CPC title