Coherent interconnect power reduction using hardware controlled split snoop directories

Patent metadata

Field	Value
Publication number	US-10606339-B2
Application number	US-201615259697-A
Country	US
Kind code	B2
Filing date	Sep 8, 2016
Priority date	Sep 8, 2016
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

First claim

What is claimed is:

1. A method of implementing multiple split snoop directories on a computing device, comprising:
enabling a first split snoop directory configured with a first tag approach snoop directory architecture for a first power domain having at least a first multi-core processor and a second split snoop directory configured with a second tag approach snoop directory architecture for a second power domain having at least a second multi-core processor, wherein the first power domain includes a plurality of processor caches and the second power domain includes at least one processor cache, and wherein the first tag approach is different from the second tag approach;
determining whether all of the plurality of processor caches in the first power domain are in a low power state; and
disabling the first split snoop directory in response to determining that all of the plurality of processor caches in the first power domain are in a low power state.

2. The method of claim 1 , further comprising:
detecting a condition for changing at least one processor cache of the plurality of processor caches in the first power domain to a low power state; and
sending a request to change the first split snoop directory to a low power state in response to detecting the condition for changing the at least one processor cache to a low power state.

3. The method of claim 2 , further comprising receiving the request to change the first split snoop directory to a low power state,
wherein determining whether all of the plurality of processor caches in the first power domain are in a low power state comprises determining whether all of the plurality of processor caches in the first power domain are in a low power state in response to receiving the request to change the first split snoop directory to a low power state.

4. The method of claim 1 , further comprising receiving a condition for changing at least one processor cache of the plurality of processor caches in the first power domain to a low power state,
wherein determining whether all of the plurality of processor caches in the first power domain are in a low power state comprises determining whether all of the plurality of processor caches in the first power domain are in a low power state in response to detecting the condition for changing the at least one processor cache to a low power state.

5. The method of claim 4 , wherein receiving a condition for changing at least one processor cache of the plurality of processor caches in the first power domain to a low power state comprises receiving a signal indicating a power state of the at least one processor cache of the plurality of processor caches in the first power domain from the first power domain.

6. The method of claim 1 , further comprising leaving the first split snoop directory enabled in response to determining that at least one processor cache of the plurality of processor caches in the first power domain is in a high power state.

7. The method of claim 1 , further comprising:
detecting a condition for changing at least one processor cache of the plurality of processor caches in the first power domain to a high power state; and
enabling the first split snoop directory in response to detecting the condition for changing the at least one processor cache to a high power state and determining that the plurality of processor caches in the first power domain are in a low power state.

8. The method of claim 7 , wherein:
a low power state includes one of an “OFF” state and a “RET” (retention) state; and
a high power state includes an “ON” state.

9. The method of claim 1 , further comprising:
enabling N split snoop directories for N power domains and M split snoop directories for M power domains, wherein N and M are integers greater than 1, the N power domains include N pluralities of processor caches and the M power domains include at least one processor cache;
determining whether all of any of the plurality of processor caches in the N power domains are in a low power state; and
disabling any of the N split snoop directories for which all of the plurality of processor caches in the N power domains are in a low power state.

10. A computing device configured to implement multiple split snoop directories, comprising:
a first power domain including a plurality of processor caches;
a second power domain including at least one processor cache;
a coherent interconnect having a first split snoop directory configured with a first tag approach snoop directory architecture for the first power domain having at least a first multi-core processor and a second split snoop directory configured with a second tag approach snoop directory architecture for the second power domain having at least a second multi-core processor, wherein the first tag approach is different from the second tag approach;
a first processing device communicatively connected to the first power domain and communicatively connected to the coherent interconnect; and
a second processing device communicatively connected to the second power domain and communicatively connected to the coherent interconnect,
wherein the first processing device is configured to perform operations comprising:
enabling the first split snoop directory;
determining whether all of the plurality of processor caches in the first power domain are in a low power state; and
disabling the first split snoop directory in response to determining that all of the plurality of processor caches in the first power domain are in a low power state.

11. The computing device of claim 10 , further comprising a third processing device communicatively connected to the first power domain and communicatively connected to the first processing device, the third processing device configured to perform operations comprising:
detecting a condition for changing at least one processor cache of the plurality of processor caches in the first power domain to a low power state; and
sending a request to the first processing device to change the first split snoop directory to a low power state in response to detecting the condition for changing the at least one processor cache to a low power state.

12. The computing device of claim 11 , wherein the first processing device is configured to perform operations further comprising receiving the request to change the first split snoop directory to a low power state,
wherein the first processing device is configured to perform operations such that determining whether all of the plurality of processor caches in the first power domain are in a low power state comprises determining whether all of the plurality of processor caches in the first power domain are in a low power state in response to receiving the request to change the first split snoop directory to a low power state.

13. The computing device of claim 10 , wherein the first processing device is configured to perform operations further comprising receiving a condition for changing at least one processor cache of the plurality of processor caches in the first power domain to a low power state,
wherein the first processing device is configured to perform operations such that determining whether all of the plurality of processor caches in the first power domain are in a low power state comprises determining whether all of the plurality of processor caches in the first power domain are in a low power state in response to detecting the condition for changing the at least one processor cache to a low power state.

14. The computing device of claim 13 , wherein the first processing device is configured to perform operations such t

Assignees

• Qualcomm Inc

Inventors

• Avoinne Christophe
• Montperrus Luc
• Boucard Philippe
• Gupta Rakesh Kumar

Classifications

• G06F12/0833 Primary

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F9/54

  Interprogram communication · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title