Establishing system on chip root of trust from multiple chiplet roots of trust
US-2025315512-A1 · Oct 9, 2025 · US
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Asbe Samar patents
Asbe Samar is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Asbe Samar |
| Total patents | 21 |
| First publication | May 7, 2015 |
| Latest publication | Oct 9, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Hardware identity impersonation for target access control
US-12432204-B2 · Sep 30, 2025 · US
Establishing system on chip root of trust from multiple chiplet roots of trust
US-12373535-B2 · Jul 29, 2025 · US
Coherent key management across multiple chiplets
US-2025097019-A1 · Mar 20, 2025 · US
Establishing system on chip root of trust from multiple chiplet roots of trust
US-2025061181-A1 · Feb 20, 2025 · US
Multistage device boot with independent stage keys
US-2025053659-A1 · Feb 13, 2025 · US
Hardware identity impersonation for target access control
US-2024106824-A1 · Mar 28, 2024 · US
Access control system and method for isolating mutually distrusting security domains
US-11783042-B2 · Oct 10, 2023 · US
Access control system and method for isolating mutually distrusting security domains
US-2021397714-A1 · Dec 23, 2021 · US
Policy based access control of subsystem assets via external debug interface
US-2021365557-A1 · Nov 25, 2021 · US
Recent patents
Latest publications not already listed above.
Optimizing headless virtual machine memory management with global translation lookaside buffer shootdown
US-10725932-B2 · Jul 28, 2020 · US
Method and apparatus for establishing system-on-chip (SOC) security through memory management unit (MMU) virtualization
US-10514943-B2 · Dec 24, 2019 · US
Optimizing headless virtual machine memory management with global translation lookaside buffer shootdown
US-2019163645-A1 · May 30, 2019 · US
Providing hardware-based translation lookaside buffer (TLB) conflict resolution in processor-based systems
US-10228991-B2 · Mar 12, 2019 · US
System Memory Management Unit Architecture For Consolidated Management Of Virtual Machine Stage 1 Address Translations
US-2019026231-A1 · Jan 24, 2019 · US
Mechanisms to enforce security with partial access control hardware offline
US-2019012271-A1 · Jan 10, 2019 · US
Providing hardware-based translation lookaside buffer (tlb) conflict resolution in processor-based systems
US-2019004883-A1 · Jan 3, 2019 · US
Method and apparatus for establishing system-on-chip (soc) security through memory management unit (mmu) virtualization
US-2018136967-A1 · May 17, 2018 · US
Secure, fast and normal virtual interrupt direct assignment in a virtualized interrupt controller in a mobile system-on-chip
US-9355050-B2 · May 31, 2016 · US
Apparatus and method for inheriting a non-secure thread context
US-9342688-B2 · May 17, 2016 · US
Secure, Fast and Normal Virtual Interrupt Direct Assignment in a Virtualized Interrupt Controller in a Mobile System-On-Chip
US-2015127866-A1 · May 7, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 21 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F21/57 | 7 |
| G06F9/45558 | 7 |
| G06F21/575 | 6 |
| G06F12/1027 | 6 |
| G06F21/572 | 4 |