Establishing system on chip root of trust from multiple chiplet roots of trust

Patent metadata

Field	Value
Publication number	US-12373535-B2
Application number	US-202318452209-A
Country	US
Kind code	B2
Filing date	Aug 18, 2023
Priority date	Aug 18, 2023
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

Systems and techniques are provided for establishing a connection. For instance, a process may include receiving, by a first root of trust (C-ROT) of a first chiplet of a plurality of chiplets from a second C-RoT of a second chiplet, a second certificate along with security state information and debug information for the second chiplet; authenticating a security state and a debug state of the second chiplet based on the security state information and the debug information; authenticating the second certificate; and establishing a security boundary with the second chiplet.

First claim

What is claimed is:

1. An electronic device, comprising:
a memory system; and
a processor system coupled to the memory system, the processor system including a plurality of chiplets, wherein a first chiplet of the plurality of chiplets includes a first chiplet root of trust (C-RoT) and is configured to:
receive, from a second C-ROT of a second chiplet, a second certificate along with security state information and debug information for the second chiplet;
authenticate a security state and a debug state of the second chiplet based on the security state information and the debug information;
authenticate the second certificate; and
establish a security boundary with the second chiplet.

2. The electronic device of claim 1 , wherein the first chiplet is further configured to receive a first certificate as a part of fabricating the first chiplet.

3. The electronic device of claim 2 , wherein the first chiplet is further configured to:
determine, by the first C-ROT of the first chiplet, a first security state and a first debug state for the first chiplet; and
transmit the first certificate, information about the first security state, and information about the first debug state to the second chiplet for authentication.

4. The electronic device of claim 3 , wherein the first chiplet is further configured to receive, from the second chiplet, an indication that the first chiplet has been authenticated, wherein the security boundary is established based on the indication that the first chiplet has been authenticated, the authentication of the security state and debug state, and the authentication of the second certificate.

5. The electronic device of claim 4 , wherein, to authenticate the security state and debug state of the second chiplet, the first chiplet is configured to:
match the first security state to the security state information; and
match the first debug state to the debug information.

6. The electronic device of claim 1 , wherein the security boundary is established as a part of a boot process for the processor system.

7. The electronic device of claim 6 , wherein the first chiplet is further configured to:
receive a first pairing key as a part of a provisioning procedure for the processor system;
receive authentication information associated with a second pairing key from the second chiplet, wherein the second pairing key is received by the second chiplet as a part of the provisioning procedure; and
maintain the security boundary by verifying the authentication information based on the first pairing key.

8. The electronic device of claim 7 wherein the security boundary is maintained after the boot process for the processor system.

9. The electronic device of claim 1 , wherein the processor system includes a plurality of platforms and wherein the first chiplet and second chiplet are in a platform of the plurality of platforms.

10. The electronic device of claim 9 , wherein each platform, of the plurality of platforms, includes at least two chiplets.

11. A method for secure processing, comprising:
receiving, by a first root of trust (C-RoT) of a first chiplet of a plurality of chiplets from a second C-ROT of a second chiplet, a second certificate along with security state information and debug information for the second chiplet;
authenticating a security state and a debug state of the second chiplet based on the security state information and the debug information;
authenticating the second certificate; and
establishing a security boundary with the second chiplet.

12. The method of claim 11 , further comprising receiving, by the first C-ROT a first certificate as a part of fabricating the first chiplet.

13. The method of claim 12 , further comprising:
determining, by the first C-ROT of the first chiplet, a first security state and a first debug state for the first chiplet; and
transmitting the first certificate, information about the first security state, and information about the first debug state to the second chiplet for authentication.

14. The method of claim 13 , further comprising receiving, from the second chiplet, an indication that the first chiplet has been authenticated, wherein the security boundary is established based on the indication that the first chiplet has been authenticated, the authentication of the security state and debug state, and the authentication of the second certificate.

15. The method of claim 14 , wherein, authenticating the security state and debug state of the second chiplet comprises:
matching the first security state to the security state information; and
matching the first debug state to the debug information.

16. The method of claim 11 , wherein the security boundary is established as a part of a boot process for the plurality of chiplets.

17. The method of claim 16 , further comprising:
receiving a first pairing key as a part of a provisioning procedure the plurality of chiplets;
receiving authentication information associated with a second pairing key from the second chiplet, wherein the second pairing key is received by the second chiplet as a part of the provisioning procedure; and
maintaining the security boundary by verifying the authentication information based on the first pairing key.

18. The method of claim 17 wherein the security boundary is maintained after the boot process for the plurality of chiplets.

19. The method of claim 11 , wherein a processor system includes a plurality of platforms and wherein the first chiplet and second chiplet are in a platform of the plurality of platforms.

20. The method of claim 19 , wherein each platform, of the plurality of platforms, includes at least two chiplets.

21. A non-transitory computer-readable medium having stored thereon instructions that, when executed by a first chiplet of a plurality of chiplets, cause the first chiplet to:
receive, by a first root of trust (C-RoT) of the first chiplet from a second C-ROT of a second chiplet, a second certificate along with security state information and debug information for the second chiplet;
authenticate a security state and a debug state of the second chiplet based on the security state information and the debug information;
authenticate the second certificate; and
establish a security boundary with the second chiplet.

22. The non-transitory computer-readable medium of claim 21 , wherein the instructions cause the first chiplet to receive a first certificate as a part of fabricating the first chiplet.

23. The non-transitory computer-readable medium of claim 22 , wherein the instructions cause the first chiplet to:
determine, by the first C-ROT of the first chiplet, a first security state and a first debug state for the first chiplet; and
transmit the first certificate, information about the first security state, and information about the first debug state to the second chiplet for authentication.

24. The non-transitory computer-readable medium of claim 23 , wherein the instructions cause the first chiplet to receive, from the second chiplet, an indication that the first chiplet has been authenticated, wherein the security boundary is established based on the indication that the first chiplet has been authenticated, the authentication of the security state and debug state, and the authentication of the second certificate.

25. The non-transitory computer-readable medium of claim 24 , wherein, to authenticate the security state and d

Assignees

• Qualcomm Inc

Inventors

• Ragavan Rengarajan
• Gao Changjian
• Asbe Samar
• Hongal Shivaprasad
• Pochuev Denis
• Bass Richard Wesley
• Dosi Priyanka

Classifications

• G06F21/64

  Protecting data integrity, e.g. using checksums, certificates or signatures · CPC title

• G06F21/575

  Secure boot · CPC title

• H04L63/0823

  using certificates (cryptographic mechanisms or cryptographic arrangements for entity authentication involving certificates H04L9/3263) · CPC title

• G06F21/445

  by mutual authentication, e.g. between devices or programs · CPC title

• G06F21/33 Primary

  using certificates · CPC title