Secure, fast and normal virtual interrupt direct assignment in a virtualized interrupt controller in a mobile system-on-chip

US9355050B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9355050-B2
Application numberUS-201314072201-A
CountryUS
Kind codeB2
Filing dateNov 5, 2013
Priority dateNov 5, 2013
Publication dateMay 31, 2016
Grant dateMay 31, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for assigning one or more interrupts in a computing device, comprising: running, by a first processor, a high level operating system guest virtual machine; running, by a second processor, a virtual machine monitor; storing, by an interrupt direct assignment control register, a direct assignment control value; storing, by an interrupt direct assignment register, interrupt direct assignment values of interrupts; routing, by an interrupt distributor, the interrupt to a trusted execution environment when a configuration of an interrupt identifier indicates an associated security level; correlating, by the interrupt distributor, an interrupt direct assignment value with the interrupt, wherein the interrupt direct assignment value indicates an owner of the interrupt; routing, by the interrupt distributor, the interrupt to a high level operating system guest virtual machine as a fast virtual interrupt or a normal virtual interrupt when the interrupt direct assignment value indicates the high level operating system guest is the owner of the interrupt; and routing, by the interrupt distributor, the interrupt to a virtual machine monitor when the assignment value indicates the virtual machine monitor is the owner of the interrupt. 2. The method of claim 1 , further comprising checking for an available spot in an interrupt list when the interrupt direct assignment value indicates the high level operating system guest is the owner of the interrupt, wherein routing the interrupt to the high level operating system guest virtual machine comprises: routing the interrupt to the high level operating system guest virtual machine when there is the available spot in the interrupt list bypassing the virtual machine monitor; and routing the interrupt to the virtual machine monitor when the interrupt list is occupied. 3. The method of claim 2 , further comprising disabling correlating the interrupt direct assignment value to the interrupt when the interrupt list is occupied. 4. The method of claim 1 , wherein: the interrupt direct assignment value further indicates a priority of the interrupt; routing the interrupt to the high level operating system guest virtual machine comprises routing the interrupt as a virtual interrupt corresponding to a physical interrupt, the virtual interrupt having a virtual interrupt identification being the same as a physical interrupt identification of the corresponding physical interrupt; and routing the interrupt to the virtual machine monitor comprises routing the interrupt as the physical interrupt. 5. The method of claim 4 , wherein: the priority of the interrupt comprises a fast interrupt and a normal interrupt; routing the interrupt to the high level operating system guest virtual machine further comprises: routing the interrupt to a first interrupt interface dedicated for fast virtual interrupts when the interrupt is the fast interrupt; and routing the interrupt to a second interrupt interface dedicated for normal virtual interrupts when the interrupt is the normal interrupt. 6. The method of claim 1 , wherein the configuration of the interrupt identifier comprises an interrupt security group value, the method further comprising: correlating the interrupt security group value with the interrupt, wherein the interrupt security group value indicates an interrupt type; and determining whether the interrupt is a secure interrupt type or a non-secure interrupt type, wherein routing the interrupt to the trusted execution environment when the configuration of the interrupt identifier indicates the associated security level comprises routing the interrupt to the trusted execution environment on a processor when the interrupt security group value indicates the interrupt is of the secure interrupt type, and wherein correlating the interrupt direct assignment value with the interrupt comprises correlating the interrupt direct assignment value with the interrupt when the interrupt security group value indicates the interrupt is of the non-secure interrupt type. 7. The method of claim 6 , wherein: routing the interrupt to the high level operating system guest virtual machine as the fast virtual interrupt or the normal virtual interrupt when the interrupt direct assignment value indicates the high level operating system guest is the owner of the interrupt comprises routing the interrupt to a normal execution environment on the processor; and routing the interrupt to the virtual machine monitor when the assignment value indicates the virtual machine monitor is the owner of the interrupt comprises routing the interrupt to the normal execution environment on the processor. 8. A computing device, comprising: a first processor configured to run a high level operating system guest virtual machine; a second processor configured to run a virtual machine monitor; an interrupt direct assignment control register configured to store a direct assignment control value; an interrupt direct assignment register configured to store interrupt direct assignment values of interrupts; and an interrupt distributor coupled to the interrupt direct assignment control register, the interrupt direct assignment register, the first processor, and the second processor, wherein the interrupt distributor is configured to perform operations comprising: routing the interrupt to a trusted execution environment when a configuration of an interrupt identifier indicates an associated security level; correlating an interrupt direct assignment value with the interrupt, wherein the interrupt direct assignment value indicates an owner of the interrupt; routing the interrupt to the high level operating system guest virtual machine as a fast virtual interrupt or a normal virtual interrupt when the interrupt direct assignment value indicates the high level operating system guest is the owner of the interrupt; and routing the interrupt to the virtual machine monitor when the assignment value indicates the virtual machine monitor is the owner of the interrupt. 9. The computing device of claim 8 , further comprising an interrupt list register connected to the interrupt distributor configured to hold interrupt information, including an interrupt identifier, wherein the interrupt distributor is further configured to perform operations comprising checking for an available spot in the interrupt list register when the interrupt direct assignment value is configured to indicate the high level operating system guest is the owner of the interrupt, and wherein routing the interrupt to the high level operating system guest virtual machine comprises: routing the interrupt to the high level operating system guest virtual machine when there is the available spot in the interrupt list bypassing the virtual machine monitor; and routing the interrupt to the virtual machine monitor when the interrupt list is occupied. 10. The computing device of claim 9 , further comprising a control interface configured to connect the second processor and the interrupt direct assignment control register, wherein the second processor is further configured to perform operations comprising disabling the interrupt direct assignment register when the interrupt list register is occupied. 11. The computing device of claim 8 , wherein: the interrupt direct assignment value is further configured to indicate a priority of the interrupt; and the interrupt distributor is further configured to perform operations comprising: routing the interrupt to the high level operating system guest virtual machine as a virtual interrupt corresponding to a physical interrupt, the virtual interrupt having a virtual inter

Assignees

Inventors

Classifications

  • I/O management, e.g. providing access to device drivers or storage · CPC title

  • using interrupt (G06F13/32 takes precedence) · CPC title

  • by interrupt, e.g. masked · CPC title

  • Hypervisor-specific management and integration aspects · CPC title

  • G06F13/26Primary

    with priority control · CPC title

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What does patent US9355050B2 cover?
Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interr…
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification G06F13/26. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 31 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).