Integrated chip and manufacturing method therefor, and full-color integrated chip and display panel
US-12183868-B2 · Dec 31, 2024 · US
Chip identification pattern and method of forming
US9136222B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136222-B2 |
| Application number | US-201213469386-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 11, 2012 |
| Priority date | May 11, 2012 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable identifier. In some cases, the method includes: exposing a level of an integrated circuit (IC) chip using a first mask orientation; subsequently exposing the level of the IC chip using a second mask orientation distinct from the first mask orientation; and developing the level of the IC chip to form an electrically measurable identifier on the IC chip.
First claim
Opening claim text (preview).
We claim: 1. A method comprising: overlaying a first mask, at a first orientation, over a level of an integrated circuit (IC) chip, wherein the level of the IC chip includes a photosensitive material; exposing the level of the IC chip, through the first mask, to a light source to form a first pattern in the level of the IC chip; overlaying the first mask, at a second orientation distinct from the first orientation, over the level of the IC chip after the exposing to form the f…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W46/00Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136222B2 cover?
- Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable identifier. In some cases, the method includes: exposing a level of an integrated circuit (IC) chip using a first mask orientation; subsequently exposing the level of the IC chip using a second mask orie…
- Who is the assignee on this patent?
- Amoah Yoba, Ellis-Monaghan John J, Kuo Roger C, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10W46/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).