Ring structures in device die

Patent metadata

Field	Value
Publication number	US-2015348916-A1
Application number	US-201414467698-A
Country	US
Kind code	A1
Filing date	Aug 25, 2014
Priority date	May 30, 2014
Publication date	Dec 3, 2015
Grant date	—

Abstract

A die includes a metal pad, a passivation layer over the metal pad, and a polymer layer over the passivation layer. A metal pillar is over and electrically coupled to the metal pad. A metal ring is coplanar with the metal pillar. The polymer layer includes a portion coplanar with the metal pillar and the metal ring.

First claim

What is claimed is:

1 . A structure comprising:
a die comprising:
a first metal pad;
a passivation layer over the first metal pad;
a polymer layer over the passivation layer;
a metal pillar over and electrically coupled to the first metal pad; and
a metal ring coplanar with the metal pillar, wherein the polymer layer comprises a first portion coplanar with the metal pillar and the metal ring.

2 . The structure of claim 1 further comprising a second metal pad coplanar with the first metal pad, wherein the second metal pad forms an additional metal ring adjacent to edges of the die.

3 . The structure of claim 2 , wherein the metal ring extends into the passivation layer, with a bottom surface of the metal ring in contact with a top surface of the second metal pad.

4 . The structure of claim 2 , wherein the metal ring comprises a bottom surface in contact with a top surface of the passivation layer, with the metal ring fully separated from the second metal pad.

5 . The structure of claim 1 , wherein the metal ring is electrically floating.

6 . The structure of claim 1 further comprising a seal ring overlapped by the metal ring, wherein the seal ring extends into a plurality of Inter-Metal Dielectric (IMD) layers.

7 . The structure of claim 1 further comprising:
a molding material molding the die therein;
a plurality of through-vias penetrating through the molding material;
a dielectric layer with a surface contacting the molding material; and
redistribution lines in the dielectric layer and electrically coupled to the metal pillar and the plurality of through-vias, wherein the metal ring comprises a surface coplanar with the surface of the dielectric layer, and wherein an entirety of the surface of the metal ring is in contact with the dielectric layer.

8 . The structure of claim 1 , wherein the polymer layer further comprises a second portion and a third portion overlapping the metal pillar and the metal ring, respectively.

9 . A structure comprising:
a die comprising:
a first metal pad;
a second metal pad coplanar with the first metal pad, wherein the second metal pad forms a ring encircling the first metal pad;
a passivation layer over the first metal pad and the second metal pad, with the passivation layer comprising an opening aligned to a center portion of the first metal pad;
a polymer layer over the passivation layer;
a metal pillar over and electrically coupled to the first metal pad;
a metal ring coplanar with the metal pillar, with the metal ring encircling the metal pillar, wherein the metal ring overlaps the second metal pad; and
a seal ring underlying and overlapped by the metal ring;
a molding material surrounding the die, wherein a top surface of the molding material is coplanar with a first top surface of the metal pillar and a second top surface of the metal ring; a dielectric layer over and in contact with the molding material; and redistribution lines in the dielectric layer and electrically coupled to the metal pillar, wherein an entirety of the metal ring is covered by the dielectric layer.

10 . The structure of claim 9 , wherein no conductive feature in the dielectric layer is in contact with the metal ring.

11 . The structure of claim 9 , wherein the metal ring is in contact with the second metal pad.

12 . The structure of claim 11 , wherein the metal ring comprises a portion in the passivation layer, with a bottom surface of the portion of the metal ring in contact with the second metal pad.

13 . The structure of claim 9 , wherein the metal ring comprises a bottom surface in contact with a top surface of the passivation layer, with the metal ring fully separated from the second metal pad by the passivation layer.

14 . The structure of claim 9 , wherein the metal ring is fully insulated in dielectric materials, with all surfaces of the metal ring in contact with the dielectric materials.

15 . A method comprising:
forming a die comprising:
a metal pillar;
a metal ring coplanar with the metal pillar; and
a polymer layer comprising a first portion coplanar with the metal pillar and the metal ring, with the metal pillar and the metal ring encircled by the polymer layer;
molding the die in a molding material; and grinding the molding material to expose a first top surface of the metal pillar and a second top surface of the metal ring.

16 . The method of claim 15 further comprising:
forming a dielectric layer over and in contact with the metal pillar, the metal ring, and the molding material; and
forming redistribution lines in the dielectric layer, wherein one of the redistribution lines is connected to the metal pillar, and after the redistribution lines are formed, an entirety of the second top surface of the metal ring is in contact with a bottom surface of the dielectric layer.

17 . The method of claim 16 , wherein after the redistribution lines are formed, no metal feature in the dielectric layer is in contact with the metal ring.

18 . The method of claim 15 further comprising forming through-vias in the molding material, wherein after the grinding the molding material, the through-vias are exposed.

19 . The method of claim 15 , wherein the metal ring is formed to overlap a seal ring in the die.

20 . The method of claim 19 , wherein a bottom surface of the metal ring is in contact with the seal ring.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chen Ying-Ju
• Chen Jie
• Chen Hsien-Wei

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title