Memory-aware matrix factorization

Patent metadata

Field	Value
Publication number	US-9626736-B2
Application number	US-201514742746-A
Country	US
Kind code	B2
Filing date	Jun 18, 2015
Priority date	Jun 18, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Embodiments include method, systems and computer program products for performing memory-aware matrix factorization on a graphics processing unit. Aspects include determining one or more types of memory on the graphics processing unit and determining one or more characteristics of each of the one or more types of memory. Aspects also include assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics and executing the matrix factorization algorithm on the graphics processing unit.

First claim

What is claimed is:

1. A computer program product for performing memory-aware matrix factorization on a graphics processing unit, the computer program product comprising:
a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
determining one or more types of memory on the graphics processing unit;
determining one or more characteristics of each of the one or more types of memory;
assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics; and
executing the matrix factorization algorithm on the graphics processing unit,
wherein the one or more types of memory include a register memory, a cache memory and a global memory and wherein the cache memory includes a shared memory and a texture memory, wherein the texture memory is read-only.

2. The computer program product of claim 1 , wherein the assignment of the plurality of memory accesses is configured to store hotspot variables in the cache memory.

3. The computer program product of claim 1 , wherein the characteristics include at least one of a memory size, an access latency, and a read/write permission.

4. The computer program product of claim 1 , wherein the texture memory is used to store cached entries from the global memory.

5. The computer program product of claim 1 , wherein the texture memory is used to cache read-only entries from the global memory.

6. A graphics processing unit for performing memory-aware matrix factorization, comprising:
a processor in communication with one or more types of memory, the processor configured to:
determine the one or more types of memory on the graphics processing unit;
determine one or more characteristics of each of the one or more types of memory;
assign each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics; and
execute the matrix factorization algorithm on the graphics processing unit,
wherein the one or more types of memory include a register memory, a cache memory and a global memory and wherein the cache memory includes a shared memory and a texture memory, wherein the texture memory is read-only.

7. The graphics processing unit of claim 6 , wherein the one or more types of memory include a register memory, a cache memory and a global memory.

8. The graphics processing unit of claim 6 , wherein the assignment of the plurality of memory accesses is configured to store hotspot variables in the cache memory.

Assignees

• IBM

Inventors

• Cao Liangliang
• Fong Liana L
• Tan Wei

Classifications

• G06T1/60 Primary

  Memory management · CPC title

• G06F3/0601

  Interfaces specially adapted for storage systems · CPC title

• G06F8/443

  Optimisation · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F2212/302

  In image processor or graphics adapter · CPC title