System and method for pipelined time-domain computing using time-domain flip-flops and its application in time-series analysis
US-11467831-B2 · Oct 11, 2022 · US
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Additive or subtractive mixing of two pulse rates into one (beat-frequency oscillators H03B21/00; input circuits of electric counters, e.g. up-down counters H03K21/00)
Additive or subtractive mixing of two pulse rates into one (beat-frequency oscillators H03B21/00; input circuits of electric counters, e.g. up-down counters H03K21/00) · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F7/605 |
| Official title | {Additive or subtractive mixing of two pulse rates into one (beat-frequency oscillators H03B21/00; input circuits of electric counters, e.g. up-down counters H03K21/00)} |
| Display label | Additive or subtractive mixing of two pulse rates into one (beat-frequency oscillators H03B21/00; input circuits of electric counters, e.g. up-down counters H03K21/00) |
| Total patents | 17 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 2 |
| 2016 | 1 |
| 2017 | 2 |
| 2018 | 3 |
| 2019 | 2 |
| 2020 | 3 |
| 2021 | 2 |
| 2022 | 2 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
System and method for pipelined time-domain computing using time-domain flip-flops and its application in time-series analysis
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Software reconfigurable digital phase lock loop architecture
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Software reconfigurable digital phase lock loop architecture
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Pulsed based arithmetic units
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Software reconfigurable digital phase lock loop architecture
US-2018083644-A1 · Mar 22, 2018 · US
Phase domain calculator clock, ALU, memory, register file, sequencer, latches
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Software reconfigurable digital phase lock loop architecture
US-2017005666-A1 · Jan 5, 2017 · US
Software reconfigurable digital phase lock loop architecture
US-9473155-B2 · Oct 18, 2016 · US
Software reconfigurable digital phase lock loop architecture
US-2015318861-A1 · Nov 5, 2015 · US
ASIP with reconfigurable circuitry implementing atomic operations of a PLL
US-9116769-B2 · Aug 25, 2015 · US