Counting elements in neural network input data

Patent metadata

Field	Value
Publication number	US-11734002-B2
Application number	US-201916697687-A
Country	US
Kind code	B2
Filing date	Nov 27, 2019
Priority date	Apr 19, 2017
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

The present disclosure provides a counting device and counting method. The device includes a storage unit, a counting unit, and a register unit, where the storage unit may be connected to the counting unit for storing input data to be counted and storing a number of elements satisfying a given condition in the input data after counting; the register unit may be configured to store an address where input data to be counted is stored in the storage unit; and the counting unit may be connected to the register unit, and may be configured to acquire a counting instruction, read a storage address of the input data to be counted in the register unit according to the counting instruction, acquire corresponding input data to be counted in the storage unit, perform statistical counting on a number of elements in the input data to be counted that satisfy the given condition, and obtain a counting result. The counting device and the method may improve the computation efficiency by writing an algorithm of counting a number of elements that satisfy a given condition in input data into an instruction form.

First claim

What is claimed is:

1. A counting device, comprising:
a storage circuit configured to store input data to be counted and store a count of elements in the input data that satisfy a given condition after counting;
a register circuit is configured to store an address in the storage circuit where the input data to be counted is stored; and
a counting circuit connected to the register circuit and the storage circuit wherein the counting circuit is configured to:
acquire a counting instruction,
read a storage address of the input data in the register circuit according to the counting instruction,
acquire corresponding input data to be counted in the storage circuit,
identifying elements in the input data that satisfy the given condition, and
obtain a counting result,

wherein the counting circuit includes: an input/output circuit, a computation circuit, and an accumulator circuit,
wherein the input/output circuit is connected to the computation circuit and is configured to retrieve a portion of data of a set length from the input data to be counted, and transmitting the portion of data to the computation circuit,
wherein the computation circuit includes an adder configured to add a number of respective elements in the portion of data of the set length that satisfy the given condition, and output an obtained result to the accumulator circuit, and
wherein the accumulator circuit is configured to accumulate the result obtained by the computation circuit.

2. The counting device of claim 1 , wherein the storage circuit is main storage, and/or a cache.

3. The counting device of claim 1 , wherein, the given condition includes:
at least one element in the portion of data of the set length is the same as a given element, or
at least one element in the portion data of the set length are within a set range.

4. The counting device of claim 1 , wherein the computation circuit further includes:
a determination sub-module configured to
determine whether at least one element in the portion of data of the set length satisfies the given condition,
output 1 based on a determination that at least one element in the portion of data satisfies the condition, and
output 0 based on a determination that no element in the portion of data satisfies the condition, and
send one or more values output as 1 to the adder for accumulation.

5. The counting device of claim 1 , wherein a structure of the adder includes n layers, wherein: a first layer includes l full adders, a second layer includes ┌2l/3┐ full adders, . . . a m th layer includes ┌2 m−1 /3 m−1 ┐ full adders, wherein l, m, and n are integers greater than 1, m is an integer greater than 1 and less than n, and ┌x┐ represents that data x is subjected to a ceiling operation.

6. The counting device of claim 1 ,
wherein the counting circuit is structured as a multi-stage pipeline,
wherein operations of reading a vector in the input/output circuit are performed at a first pipeline stage, the computation circuit is at a second pipeline stage, and the accumulator circuit is at a third pipeline stage.

7. The counting device of claim 1 ,
wherein the counting instruction includes an opcode and one or more operation fields,
wherein the opcode indicates that the instruction is a counting instruction, and the counting circuit performs a counting computation in accordance with the opcode; and
wherein the operation fields include address information in the counting instruction for the input data to be counted, and/or address information of the given condition.

8. The counting device of claim 1 , further comprising:
an instruction memory configured to store a counting instruction;
an instruction processing circuit connected to the instruction memory for acquiring the counting instruction from the instruction memory, and processing the counting instruction;
an instruction caching circuit (cache, buffer, or scratch pad) connected to the instruction processing circuit for sequentially storing counting instructions to be executed and in execution, and the instruction caching circuit is further connected to the counting circuit and the storage circuit for submitting a counting instruction after being executed and a counting result to the storage circuit; and
a dependency processing circuit connected to the instruction processing circuit for determining whether input data required for a counting instruction is up-to-date before the counting circuit acquires the counting instruction, and if the counting instruction is up-to-date, providing the counting instruction to the counting circuit directly, if the counting instruction is not up-to-date, storing the counting instruction in a storage queue of the dependency processing circuit, and after the required input data is updated, providing the counting instruction in the storage queue to the counting circuit,
wherein during a process that the counting instruction is sent from the instruction processing circuit to the dependency processing circuit, the counting instruction reads an address of the input data in the storage circuit from the register circuit.

9. The counting device of claim 8 , wherein, the instruction processing circuit includes:
an instruction fetching circuit connected to the instruction memory for acquiring a counting instruction from the instruction memory,
a decoding circuit connected to the fetching circuit for decoding the obtained counting instruction, and
an instruction queue memory for sequentially storing a decoded counting instruction, and sequentially transmitting instructions to the instruction caching circuit and the dependency processing circuit.

10. The counting device of claim 9 , wherein the instruction caching circuit is a reordering caching circuit.

11. The counting device of claim 1 , wherein a data type of the input data to be counted is a 0/1 vector, a numeric vector, or a matrix.

12. A counting method, comprising:
storing, by a storage circuit, input data to be counted and a count of elements in the input data that satisfy a given condition after counting;
storing, by a register circuit, an address in the storage circuit where the input data is stored;
acquiring, by a counting circuit, a counting instruction;
reading, by the counting circuit, a storage address of the input data to be counted in the register circuit according to the counting instruction;
acquiring, by the counting circuit, corresponding input data to be counted in the storage circuit;
identifying, by the counting circuit, elements in the input data that satisfy the given condition; and
obtaining a counting result,
wherein, the reading the storage address of the input data to be counted in the register circuit according to the counting instruction, acquiring corresponding input data to be counted in the storage circuit, and performing statistical counting on a number of elements in the input data to be counted that satisfy the given condition includes:
retrieving, by the input/output circuit, a portion of data of a set length of the input data in the storage circuit;
transmitting, by the input/output circuit, the portion of data to the computation circuit,
adding, by an adder of the computation circuit, a number of respective elements in the portion of data of the set length that satisfy the given condition;
transmitting an obtained result to the accumulator circuit; and
accumulating, by the accumulator circuit, the result obtained by the computation circuit.

13. The counting method of claim 12 , wherein the storage circuit is main storage, and/or a cache.

14. The counting method of claim 12 , further comprising:
determin

Assignees

• Shanghai Cambricon Inf Tech Co Ltd

Inventors

• Chen Tianshi
• Wei Jie
• Zhi Tian
• Wang Zai

Classifications

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F7/505

  in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title